PROCESS FLOW OF CS-24

Report
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Semiconductor
Technology and Application
吳振銘
台積電六廠製程整合部經理
2010/03/24
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
Semiconductor Brings Fun to Your Life
- History, Application and Market

What is Transistor
 How is IC Fabricated
- Process Modules
- IC Process Flow
- Technology Evolution

What the Semiconductor Fabs Care
- Yield improvement
- PFA methodology
- Defect Engineering
- Reliability
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A Day’s Work in tsmc
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Semiconductor Brings Fun to Your Life
- History, Application and Market
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What is Transistor
 How is IC Fabricated
- Process Modules
- IC Process Flow
- Technology Evolution

What the Semiconductor Fabs Care
- Yield improvement
- PFA methodology
- Defect Engineering
- Reliability
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A Day’s Work in tsmc
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Biggest Semiconductor Players
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Semiconductor Brings Fun to Your Life
- History, Application and Market

What is Transistor
 How is IC Fabricated
- Process Modules
- IC Process Flow
- Technology Evolution

What the Semiconductor Fabs Care
- Yield improvement
- PFA methodology
- Defect Engineering
- Reliability
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A Day’s Work in tsmc
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4 Types of Etch
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Wet etch
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Physical dry etch
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Chemical dry etch
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Chemical + Physical
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Technology Evolution
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00 ITRS
Technology Generation (nm)
130
01 ITRS
90
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05 ITRS
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TSMC
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‘00
‘02
‘04
‘06
‘08
‘10
‘12
ITRS: International Technology Roadmap for Semiconductors
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
Semiconductor Brings Fun to Your Life
- History, Application and Market

What is Transistor
 How is IC Fabricated
- Process Modules
- IC Process Flow
- Technology Evolution

What the Semiconductor Fabs Care
- Yield improvement
- PFA methodology
- Defect Engineering
- Reliability

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A Day’s Work in tsmc
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Imperfect Fabrication Process
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• Mask making
dust, focusing
• Growing oxide
warping in furnace, uneven reactions
• Resist
over exposure, not hardened enough
• Etching
overetch of resist and/or oxide
• Lateral diffusion
affects transistor channel lengths
• Multiple layers
mask alignment
• Packaging
bonding wires to pins of package
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Yield Improvement
• Defect reduction
• Process window characterization
• Process weakness
• Sweet spot
• Hardware control / PM / Lifetime
• Design improvement
• Innovation
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Manufacturing
 6 M a n u fa c tu rin g
O p e ra tio n M o d u le
 W a fe r P ro d u c tio n P la n n in g
 O n T im e D e live ry
 M a n a g e /P re d ic t W IP
P ro file
 C a p a c ity M a n a g e m e n t
 Im p ro ve T o o l
P ro d u c tivity
 M a n a g e S h o p F lo o r
S c h e d u lin g &
D is p a tc h in g
P la n n in g
M o d u le
 D L D a ily M a n a g e m e n t
 D L P e rfo rm a n c e
Enhancem ent
 D L E ffic ie n c y Im p ro ve m e n t
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M FG
 P ro d u c tio n C yc le T im e
C o n tro l
C IM
 C o m p u te r In te g ra tio n
M a n u fa c tu rin g
 A u to m a tio n M a te ria l
H a n d lin g S ys te m
 In te g ra te d F a c to ry
A u to m a tio n
T ps
 D L & ID L R e c ru itin g ,
T ra in in g , R e ta in in g &
In s p irin g
 Q u a lity S y s te m
M a n a g e m e n t & L o g is tic
S u p p o rt
Process Integration Engineer
 Technology readiness
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Wafer In-Process
 New technology development
 New product & experiment
 Process parameters/SPEC setting
 Product and Process qualification
 Quality Guarantee
 PCM (Process Control Monitor)
 Cpk improvement
 Defect inspection and reduction
 Cp/FT yield improvement
 Customer satisfaction
Process Related and
Modules
FEOL
BEOL
Photo
Etch
Thin Film
Diffusion
Ion Implantation
CMP
Clean
Multilevel Interconnect
STI, Salicide
Contact/ Via, Metal
Passivation
Alignment mark
Q-time, Rework, KLA
Process control CD, overlay,
thickness
Device/ Product
characteristic
WAT & QC outgoing
inspection
 Customer satisfaction index
 Engineering notice and lot handling
Customer satisfaction
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How We Work on Fast Time-to-Market
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Business Engagement
 Customized request
 MKT/RD/Fab Joint discussion
 New Tech/tool selection
 Fab’s Super Highway Service
Ramp Up
Development
 RD/Fab Joint Technology Meetings
(Yield, Defect, Major issues..)
 Joint Task Forces for Critical Modules
 Enlarge Manufacturing Window
 Joint Effort for Defect Reduction
Qualification
 Joint Review for Process Frozen
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One Ramp Team: RD and Fab
1st Si Success of Customer NTOs
Continuous Yield Improvement
Capacity Build-up and Release
 Process/Product Qualification
 Process Characterization
 Process Control Review
 Manufacturing Readiness

Semiconductor Brings Fun to Your Life
- History, Application and Market

What is Transistor
 How is IC Fabricated
- Process Modules
- IC Process Flow
- Technology Evolution

What the Semiconductor Fabs Care
- Yield improvement
- PFA methodology
- Defect Engineering
- Reliability
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A Day’s Work in tsmc
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Starting/Ending on Daily Hand over
上班時間 完成交接
08:30 ~09:00
0810
下午交接 完成交接 下班時間
17:00
17:30
Daily work
EE
• H old lot review and key lots status
• T rouble tool review & recovery plan
• P roduction y ield status
• P M arrangem ent
• W A T /L ine scrap w afer review
• R T M chart review
• M 1/IM /F inal W A T or special m odule trend chart review
• S P C trend chart review
• C ustom er response
• O n -duty follow up
• U rgent case status update
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19:30
長官關心
P IE
PE
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Goal
休息
12:00
CSV
QC
MPE
PC
M FG
• H old lot review
• D aily M ove
• Inline, defect case and tool alarm review
• E fficiency index
• T ool alarm lot or C D /T H K O O C lot handling
• T /R and C y cle tim e
• T ool release status and W P H im provem ent
• T ool total capacity for W IP
• S P C trend chart review -- C D , T H K , E /R , R s
• M ake up delay W IP
• L ow y ield (dog tool) finding
• H old lots arrangem ent
• O C A P follow up
• S pecial lots support
Urgent case
handling
TSMC Job Function
Job
Function
PIE
(Process
Integration
Engineer)
PE (Process
Engineer)
EE
(Equipment
Engineers)
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Major Job Description &
Career Development
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適合系所
適合原因
量產產品製程整合,出貨規格,
良率分析及客戶服務。
研發新產品製程,規格,品質可
靠度及客戶服務。
工作須與Module , RD , QR ,
CSV..互相溝通配合,多方面學習
。
電機,電子,材
料,物理,化
工..等理工科系
。
半導體電性,物性及
工程分析背景。
研製機台的製程條件, 符合產品的
品質要求。
建立製程條件的監控方法, 管制製
程穩定性。
開發、研究、改善生產流程。
材料,化工,
物理, 化學,
...等理工相關科
系。
半導體製程的工作大
量應用材料、物理、
化學、機械性質的知
識與使用最先進的分
析儀器。
研發改造機台,符合先進製程需
求。
持續研究開發機台生產力。追求
成本下降的機會。
維護機台穩定性。
機械,電子,
電機等理工相
關科系。
高度精密的半導體設
備需要有清晰的邏輯
概念與機構、設計、
控制等相關知識,才
能發揮最大效果。
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One Vital Day in Fab
- Engineer’s Daily Life PIE
MFG
PE/EE
EKM &
Suggestion
Hand over
meeting
Production
meeting
Hand over
meeting
Cost
reduction
Trouble
shooting
Technique
Board
Yield
improvement
Customer
response
X-Dept
meeting
EN & LH
execution
SPC
improvement
Line
excursion
FCCB
Hold lots
handling
New project
& CIT
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customer
meeting
Daily
Trend chart
The TSMC Value Proposition:
Our Trinity of Strengths
客戶的成功
先進技術
• 先進技術
• 主流製程
卓越製造
客戶夥伴關係
• 產能領導者
• 立即性與彈性
• 最佳的良率與生產
週期
• 快速量產
• 專業晶圓製造模
式
• 全面性解決方案
• 客戶服務導向提
供最大整體利益
• 長期、雙贏、信
賴
產能與財務優勢
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台積公司改變世界半導體業遊戲規則
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專業的晶圓製造與服務,改變半導體業專業垂直分工的商業模式
System/IC
Design
System/IC
Design
System/IC
Design
System/IC
Design
System Design / IC
Design
設計服務
晶圓製造
(Fab)
晶圓
製造
(Fab)
晶圓製造
(Foundry)
晶圓
製造
(Fab)
台積電
晶圓製造
台積電
封裝, 測試
Before
1986
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封裝,
測試
封裝, 測試
1990s
封裝, 測試
封裝, 測試
After 2000
IP 供應商
台積公司價值鏈
客戶
核心能力
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系統
產品
設計
智財權(IP)/資料庫(Library)
電子設計自動化(EDA)
設計服務
設計執行
台積公司
核心能力
光罩
技術
製造
晶圓測試
錫鉛凸塊(Bumping)
覆晶(Flip Chip)
總測試
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後端服務
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Thank You
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