File - Muhammad Kumail Haider

Report
A System Level Implementation
of a Three Node Relay Network
What is Cooperative
Communication?
The Three Node Channel
Point to Point Simulation
Transmitter Module
Data Source
Convolution Encoding
Packetization
BPSK Modulation
Root Raised Cosine Filter
Output to AWGN channel
Transmitter
Data Source
Convolution Encoding
Packetization
BPSK Modulation
Root Raised Cosine Filter
Output to AWGN channel
1.
2.
Image stored as array
Bit-stream formed
Transmitter
Data Source
Convolution Encoding
Packetization
BPSK Modulation
Root Raised Cosine Filter
Output to AWGN channel
Transmitter
Data Source
Convolution Encoding
Packetization
BPSK Modulation
Root Raised Cosine Filter
Output to AWGN channel
Transmitter
Data Source
Convolution Encoding
Packetization
BPSK Modulation
Root Raised Cosine Filter
Output to AWGN channel
Transmitter
Data Source
Convolution Encoding
Packetization
BPSK Modulation
Root Raised Cosine Filter
Output to AWGN channel
Transmitter
Data Source
Convolution Encoding
Packetization
BPSK Modulation
Root Raised Cosine Filter
Output to AWGN channel
Modeling the Channel
Time
Delay
Noise
Random
values
Communication Channel
Receiver Module
Input from AWGN channel
Root Raised Cosine Filter
PLL and Timing Synchronizer
BPSK Demodulation
Viterbi Decoder
Data Sink
Receiver Module
Input from AWGN channel
Root Raised Cosine Filter
PLL and Timing Synchronizer
BPSK Demodulation
Viterbi Decoder
Data Sink
Receiver Module
Input from AWGN channel
Root Raised Cosine Filter
PLL and Timing Synchronizer
BPSK Demodulation
Viterbi Decoder
Data Sink
Receiver Module
Input from AWGN channel
Root Raised Cosine Filter
PLL and Timing Synchronizer
BPSK Demodulation
Viterbi Decoder
Data Sink
Receiver Module
Input from AWGN channel
Root Raised Cosine Filter
PLL and Timing Synchronizer
BPSK Demodulation
Viterbi Decoder
Data Sink
Receiver Module
Input from AWGN channel
Root Raised Cosine Filter
PLL and Timing Synchronizer
BPSK Demodulation
Viterbi Decoder
Data Sink
Cooperative Diversity
Cooperative Schemes
• Comparison of a hybrid Decode Forward-Amplify
Forward scheme with simple Amplify Forward
• Development of a novel Compress Forward
scheme
Amplify-Forward
Relay
Yr
Xs
Xr
Yd1
Sender
Receiver
Xs
Yd
Detection Rule for AF
Hybrid-Forward
Relay
Yr
Xs
Xr
Yd2
Sender
Receiver
Xs
Yd1
Relay
Try decoding the received data using CRC codes:
– If decoded correctly, encode again and send to
receiver in second time slot
– Else switch to Amplify Forward i.e. send whatever
was received in first time slot after gain correction
Decisions at the receiver
• AF mode:
+1
 ∗  + 1 ∗  ∗  ∗ /2 ≷ 0
-1
• Decode mode:
+1
 ∗  + 1 ≷ 0
-1
Compress Forward Scheme
Relay
Yr
Hard Decisions
W
Systematic
Convolutional
Codes
Orig. dumped
BPSK
Parity
Xr
Compress Forward Scheme
Receiver
recv_1
Yd1
Hard Decisions
Yd
Hard Decisions recv_2
Systematic
Convolutional
Decoder
(Viterbi
decoder)
ML
Detector
{0,1}
Received bits
Convolutional
Decoder
ML Detector for CF scheme
+1
-1
Where
Pe is found using Monte Carlo Methods, on the path from S-R-D
Hardware Implementation
Hardware Platforms Used
USRP 1
RFX 2400 Daughterboard
RFX2400 2.3-2.9 GHz Rx/Tx
System Level Diagram of the USRP Interface
Available Software Platforms
A Brief Comparison between the USRP1 and USRP2
USRP1
USRP2
Interface
USB 2.0 (32 MB/s half
duplex)
Gigabit Ethernet (1000
MBit/s)
FPGA
Altera EP1C12
Xilinx Spartan 3 2000
RF Bandwidth to/from host
8 MHz @ 16bits
25 MHz @ 16bits
Cost
$700
$1400
ADC Samples
12-bit, 64 MS/s
14-bit, 100 MS/s
DAC Samples
14-bit, 128 MS/s
16-bit, 400 MS/s
Daughterboard capacity
2 TX, 2 RX
1 TX, 1 RX
SRAM
None
1 Megabyte
Power
6V, 3A
6V, 3A
Manual Driver Interfaces
1. Tools4SDR
Developed By : Supelec, France
Issues: Poor Data Reception
& Offline Processing
2. Simulink USRP
Developed By : KIT, Germany
Issues: Driver Compiling Issues
3. Simulink UHD
Developed By : KIT, Germany
No Issues: No Compiling Issues/Blocks available in Simulink
Hardware Parameters
Next Step: See Data Tx/Rx
Sent Sequence of bits 0’s & 1’s Passed From a
Raised Cosine Filter (Real Time Processing)
Observing FFT:
Debugging Issues
Hardware
•
•
Hardware Not Functioning
Properly
Verified By Testing on GNU
Software
•
•
•
Processing Limitations
Started Transmission and
Reception on Different
Hosts
Moved From Real-time to
Offline Processing
Complete Point to Point Hardware Testing
• Finally we tested the Hardware on a built in Point to
Point System with a QPSK Demo Present in Matlab
2011a.
• Demo After Presentation
Comprehensive Overview
Cooperative Communication Sproj 2011-2012
• Hardware realization of Amplify-Forward and
Decode-Forward technique
• Ubuntu as the platform
• GNU radio and GRC as software
• Python scripting also used for processing
Techniques Implemented
Amplify-Forward
Decode-Forward
Decode-forward
Amplify-forward
Relay
Node
2.
4
G
Hz
Relay
Node
(USRP1)
2.4 GHz
Source
Node
(USRP1)
Obstruction
Destination
Node
(USRP1)
Source
Node
Obstruction
Destination
Node
Objectives Achieved
• Point to Point simulation
• Hardware Configuration and Functionality
Testing
• Compress Forward simulation
Task Division
Subgroup 1
Taha
Roshaan
Hardware Testing and
Simulation
Subgroup 2
Kumail
Compress
Forward
Simulation
Harres
Point-Point
Simulation
Point to Point simulation
• Accomplished using matlab code
• The string ‘Cooperative Communications ##’
was transmitted
• Strings successfully reconstructed were
observed against varying SNRs
• Respective BERs computed
Hardware Functionality Testing
•
•
•
•
Accomplished using simulink model
The string ‘Hello World ###’ was transmitted
The reconstructed strings printed
Matlab code based testing in progress
Compress Forward simulation
• …………………….
Future Aims and Goals
•
•
•
•
Hardware completion of point to point system
Point to Point simulation of Compress Forward
Hardware Implementation of CF technique
Re-execution of Decode-Forward and AmplifyForward Techniques
• Tx/Rx in real-time using the 3-node relay
network
Future Aims and Goals
•
•
•
•
Hardware completion of point to point system
Point to Point simulation of Compress Forward
Hardware Implementation of CF technique
Re-execution of Decode-Forward and AmplifyForward Techniques
• Tx/Rx in real-time using the 3-node relay
network
Future Aims and Goals
•
•
•
•
Hardware completion of point to point system
Point to Point simulation of Compress Forward
Hardware Implementation of CF technique
Re-execution of Decode-Forward and AmplifyForward Techniques
• Tx/Rx in real-time using the 3-node relay
network
Future Aims and Goals
•
•
•
•
Hardware completion of point to point system
Point to Point simulation of Compress Forward
Hardware Implementation of CF technique
Re-execution of Decode-Forward and AmplifyForward Techniques
• Tx/Rx in real-time using the 3-node relay
network
Future Aims and Goals
•
•
•
•
Hardware completion of point to point system
Point to Point simulation of Compress Forward
Hardware Implementation of CF technique
Re-execution of Decode-Forward and AmplifyForward Techniques
• Tx/Rx in real-time using the 3-node relay
network

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