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Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić Designing Combinational Logic Circuits EE141 Integrated © Digital Circuits2nd 1 Combinational Circuits Combinational vs. Sequential Logic Combinational Logic Circuit In In Out Out Combinational Logic Circuit State Combinational Output = f(In) EE141 Integrated © Digital Circuits2nd Sequential Output = f(In, Previous In) 2 Combinational Circuits Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. EE141 Integrated © Digital Circuits2nd 3 Combinational Circuits Static Complementary CMOS VDD In1 In2 PUN InN In1 In2 InN PMOS only F(In1,In2,…InN) PDN NMOS only PUN and PDN are dual logic networks EE141 Integrated © Digital Circuits2nd 4 Combinational Circuits NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high A B X Y Y = X if A and B A X B Y Y = X if A OR B NMOS Transistors pass a “strong” 0 but a “weak” 1 EE141 Integrated © Digital Circuits2nd 5 Combinational Circuits PMOS Transistors in Series/Parallel Connection PMOS switch closes when switch control input is low A B X Y Y = X if A AND B = A + B A X B Y Y = X if A OR B = AB PMOS Transistors pass a “strong” 1 but a “weak” 0 EE141 Integrated © Digital Circuits2nd 6 Combinational Circuits Complementary CMOS Logic Style EE141 Integrated © Digital Circuits2nd 7 Combinational Circuits Example Gate: NAND EE141 Integrated © Digital Circuits2nd 8 Combinational Circuits 4-input NAND Gate Vdd VDD VDD In1 In2 In3 In4 Out In1 In2 Out In3 Out In4 GND In1 In2 In3 In4 GND In1 In2 In3 In4 EE141 Integrated © Digital Circuits2nd 9 Combinational Circuits Example Gate: NOR EE141 Integrated © Digital Circuits2nd 10 Combinational Circuits DC Characteristics of 2-Input NAND VOH = Vdd VOL = Gnd VLT: Different based on Input •11 – 01 •11 – 10 •11 -- 00 Va Vb 11 – 01: Similar to Inverter with resistor in source circuit 11 – 10: Similar to Inverter with resistor in drain circuit 11 – 00: Similar to Inverter with b’p = 2bp & b’n = 1/2bn VLT (11 10) VLT (11 01) VLT (11 00) EE141 Integrated © Digital Circuits2nd 11 Combinational Circuits DC Characteristics of 2-Input NAND Id; VLT VLT Vgs1 = VLT; Vgs2 = VLT – Vds1; VLT = Vds1 + Vds2 Vgs2 = Vds2 M2 is saturated M1 is linear M2 M1 ID b1 2 Vds1 VLT Vtn ID Parallel Combination: EE141 Integrated © Digital Circuits2nd [2(VLT Vtn )Vds1 Vds21 ] ID b2 2 [VLT Vtn Vds1 ]2 2I D b2 b1 b 2 1 b b b (VLT Vtn ) 2 ( )(VLT Vtn ) 2 2( b1 b 2 ) 2 2 1 b1 b 2 2 2 (VLT Vtn ) 2 12 Combinational Circuits DC Characteristics of 2-Input NAND VLT (11 01) VLT (11 10) Vtn bp b n (Vdd | Vtp |) 1 VLT (11 00) Vtn 2 bp 1 2 bp bn b n (Vdd | Vtp |) bp bn In design: •Set one (middle) VLT = Vdd/2 •Distribute about Vdd/2 •Make mean = Vdd/2 EE141 Integrated © Digital Circuits2nd 13 Combinational Circuits Input Pattern Effects on Delay Delay is dependent on the pattern of inputs Low to high transition Rp A Rp both inputs go low B Rn – delay is ~1/2 tr one input goes low CL – delay is ~tr B Rn Cint High to low transition both inputs go high – delay is ~2tf A one input goes low – delay is ~tf EE141 Integrated © Digital Circuits2nd 14 Combinational Circuits Delay Dependence on Input Patterns 3 Input Data Pattern Delay (psec) A=B=01 67 A=1, B=01 64 A= 01, B=1 61 0.5 A=B=10 45 0 A=1, B=10 80 A= 10, B=1 81 A=B=10 2.5 Voltage [V] 2 A=1 0, B=1 1.5 A=1, B=10 1 -0.5 0 100 200 time [ps] EE141 Integrated Circuits2nd © Digital 300 400 NMOS = 0.5m/0.25 m PMOS = 0.75m/0.25 m CL = 100 fF 15 Combinational Circuits Transistor Sizing Rp 2 A Rp B Rn 2 B 2 Rn A EE141 Integrated © Digital Circuits2nd Rp 4 B 2 CL Cint Rp 4 Cint A 1 Rn Rn A B CL 1 16 Combinational Circuits Transistor Sizing a Complex CMOS Gate A B 8 6 C 8 6 4 3 D 4 6 OUT = D + A • (B + C) A D 1 B EE141 Integrated © Digital Circuits2nd 2 2C 2 17 Combinational Circuits Fan-In Considerations A B C D A CL B C3 C C2 D C1 EE141 Integrated © Digital Circuits2nd Distributed RC model (Elmore delay) tpHL = 0.69 Reqn(C1+2C2+3C3+4CL) Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case. 18 Combinational Circuits tp as a Function of Fan-In 1250 quadratic tp (psec) 1000 Gates with a fan-in greater than 4 should be avoided. 750 tpH 500 tp L 250 tpL linear H 0 2 4 6 8 10 12 14 16 fan-in EE141 Integrated © Digital Circuits2nd 19 Combinational Circuits tp as a Function of Fan-Out tpNOR2 tpNAND2 tpINV tp (psec) 2 All gates have the same drive current. Slope is a function of “driving strength” 4 6 8 10 12 14 16 eff. fan-out EE141 Integrated © Digital Circuits2nd 20 Combinational Circuits tp as a Function of Fan-In and Fan-Out Fan-in: quadratic due to increasing resistance and capacitance Fan-out: each additional fan-out gate adds two gate capacitances to CL tp = a1FI + a2FI2 + a3FO EE141 Integrated © Digital Circuits2nd 21 Combinational Circuits Fast Complex Gates: Design Technique 1 Transistor sizing as long as fan-out capacitance dominates Progressive InN sizing CL MN In3 M3 C3 In2 M2 C2 In1 M1 C1 EE141 Integrated © Digital Circuits2nd Distributed RC line M1 > M2 > M3 > … > MN (the fet closest to the output is the smallest) Can reduce delay by more than 20%; decreasing gains as technology shrinks 22 Combinational Circuits Fast Complex Gates: Design Technique 2 Transistor ordering critical path charged CL In3 1 M3 In2 1 M2 C2 charged In1 M1 01 C1 charged delay determined by time to discharge CL, C1 and C2 EE141 Integrated © Digital Circuits2nd critical path 01 In1 M3 CLcharged In2 1 M2 C2 discharged In3 1 M1 C1 discharged delay determined by time to discharge CL 23 Combinational Circuits Fast Complex Gates: Design Technique 3 Alternative logic structures F = ABCDEFGH EE141 Integrated © Digital Circuits2nd 24 Combinational Circuits Fast Complex Gates: Design Technique 4 Isolating fan-in from fan-out using buffer insertion CL EE141 Integrated © Digital Circuits2nd CL 25 Combinational Circuits Ratioed Logic EE141 Integrated © Digital Circuits2nd 47 Combinational Circuits Ratioed Logic VDD Resistive Load VDD Depletion Load RL PDN VSS (a) resistive load PMOS Load VSS VT < 0 F In1 In2 In3 VDD F In1 In2 In3 PDN VSS (b) depletion load NMOS F In1 In2 In3 PDN VSS (c) pseudo-NMOS Goal: to reduce the number of devices over complementary CMOS EE141 Integrated © Digital Circuits2nd 48 Combinational Circuits Ratioed Logic VDD • N transistors + Load Resistive Load • VOH = V DD RL • VOL = F In1 In2 In3 RPN + RL • Assymetrical response PDN • Static power consumption VSS EE141 Integrated © Digital RPN Circuits2nd • tpL= 0.69 RLCL 49 Combinational Circuits Active Loads VDD Depletion Load VDD PMOS Load VT < 0 VSS F In1 In2 In3 PDN VSS depletion load NMOS EE141 Integrated © Digital Circuits2nd F In1 In2 In3 PDN VSS pseudo-NMOS 50 Combinational Circuits Pseudo-NMOS VDD A B C D F CL VOH = VDD (similar to complementary CMOS) V2 k 2 OL p V k V – V V – ------------- = -----– V n DD Tn OL DD Tp 2 2 V OL = VDD – V T 1 – kp 1 – ------ (assuming that V T = V Tn = VTp ) kn SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!! EE141 Integrated © Digital Circuits2nd 51 Combinational Circuits Pseudo-NMOS VTC 3.0 2.5 W/Lp = 4 Vout [V] 2.0 1.5 W/Lp = 2 1.0 0.5 W/Lp = 0.5 W/Lp = 1 W/Lp = 0.25 0.0 0.0 0.5 1.0 1.5 2.0 2.5 Vin [V] EE141 Integrated © Digital Circuits2nd 52 Combinational Circuits Improved Loads VDD M1 Enable M2 M1 >> M2 F A B C D CL Adaptive Load EE141 Integrated © Digital Circuits2nd 53 Combinational Circuits Improved Loads (2) VDD M1 VDD M2 Out A A B B Out PDN1 PDN2 VSS VSS Differential Cascode Voltage Switch Logic (DCVSL) EE141 Integrated © Digital Circuits2nd 54 Combinational Circuits DCVSL Example Out Out B B A B B A XOR-NXOR gate EE141 Integrated © Digital Circuits2nd 55 Combinational Circuits DCVSL Transient Response V olta ge [V] 2.5 AB 1.5 0.5 -0.5 0 EE141 Integrated © Digital Circuits2nd AB A,B 0.2 A,B 0.4 0.6 Time [ns] 0.8 1.0 56 Combinational Circuits Pass-Transistor Logic EE141 Integrated © Digital Circuits2nd 57 Combinational Circuits Pass-Transistor Logic Inputs B Switch Out A Out Network B B • N transistors • No static consumption EE141 Integrated © Digital Circuits2nd 58 Combinational Circuits Example: AND Gate B A B F = AB 0 EE141 Integrated © Digital Circuits2nd 59 Combinational Circuits NMOS-Only Logic 3.0 In 1.5m/0.25m VDD x Out 0.5m/0.25m 0.5m/0.25m Voltage [V] In Out 2.0 x 1.0 0.0 0 0.5 1 1.5 2 Time [ns] EE141 Integrated © Digital Circuits2nd 60 Combinational Circuits NMOS-only Switch C = 2.5V C = 2.5 V M2 A = 2.5 V A = 2.5 V B B Mn CL M1 VB does not pull up to 2.5V, but 2.5V - VTN Threshold voltage loss causes static power consumption NMOS has higher threshold than PMOS (body effect) EE141 Integrated © Digital Circuits2nd 61 Combinational Circuits NMOS Only Logic: Level Restoring Transistor VDD VDD Level Restorer Mr B A Mn M2 X Out M1 • Advantage: Full Swing • Restorer adds capacitance, takes away pull down current at X • Ratio problem EE141 Integrated © Digital Circuits2nd 62 Combinational Circuits Restorer Sizing Voltage [V] 3.0 2.0 •Upper limit on restorer size •Pass-transistor pull-down can have several transistors in stack W/Lr =1.75/0.25 W/L r =1.50/0.25 1.0 W/Lr =1.0/0.25 0.0 0 100 EE141 Integrated © Digital 200 Circuits2nd W/L r =1.25/0.25 300 Time [ps] 400 500 63 Combinational Circuits Complementary Pass Transistor Logic A A B B Pass-Transistor Network F (a) A A B B B Inverse Pass-Transistor Network B B A F B B A A B F=AB A B F=A+B F=AB AND/NAND EE141 Integrated © Digital Circuits2nd A F=AÝ (b) A A B B F=A+B B OR/NOR A F=AÝ EXOR/NEXOR 65 Combinational Circuits Solution 3: Transmission Gate C A C A B B C C C = 2.5 V A = 2.5 V B CL C=0V EE141 Integrated © Digital Circuits2nd 66 Combinational Circuits Resistance of Transmission Gate 30 2.5 V Resistance, ohms Rn 20 Rn Rp 2.5 V Vou t Rp 0V 10 Rn || Rp 0 0.0 EE141 Integrated © Digital 1.0 Circuits2nd Vou t , V 2.0 67 Combinational Circuits Pass-Transistor Based Multiplexer S S S S VDD S A VDD M2 F S M1 B S GND In1 EE141 Integrated © Digital Circuits2nd In2 68 Combinational Circuits Transmission Gate XOR B B M2 A A F M1 M3/M4 B B EE141 Integrated © Digital Circuits2nd 69 Combinational Circuits Delay in Transmission Gate Networks 2.5 2.5 V1 In 2.5 Vi Vi-1 C 0 2.5 C 0 Vn-1 Vi+1 C 0 Vn C C 0 (a) Req Req V1 In Req Vi C Vn-1 Vi+1 C C Req Vn C C (b) m Req Req Req Req Req Req In C CC C C CC C (c) EE141 Integrated © Digital Circuits2nd 70 Combinational Circuits Delay Optimization EE141 Integrated © Digital Circuits2nd 71 Combinational Circuits Transmission Gate Full Adder P VDD Ci A P A A P B VDD Ci A P Ci VDD S Sum Generation Ci P B VDD A P Co Carry Generation Ci A Setup P Similar delays for sum and carry EE141 Integrated © Digital Circuits2nd 72 Combinational Circuits Dynamic Logic EE141 Integrated © Digital Circuits2nd 73 Combinational Circuits Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors EE141 Integrated © Digital Circuits2nd 74 Combinational Circuits Dynamic Gate Clk Clk Mp off Mp on Out In1 In2 In3 Clk CL PDN 1 Out ((AB)+C) A C B Me Clk off Me on Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) EE141 Integrated © Digital Circuits2nd 76 Combinational Circuits Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL EE141 Integrated © Digital Circuits2nd 77 Combinational Circuits Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (Cin) reduced load capacitance due to smaller output loading (Cout) no Isc, so all the current provided by PDN goes into discharging CL EE141 Integrated © Digital Circuits2nd 78 Combinational Circuits Properties of Dynamic Gates Overall power dissipation usually higher than static CMOS no static current path ever exists between VDD and GND (including Psc) no glitching higher transition probabilities extra load on Clk PDN starts to work as soon as the input signals exceed VTn, so VLT, VIH and VIL equal to VTn low noise margin (NML) Needs a precharge/evaluate clock EE141 Integrated © Digital Circuits2nd 79 Combinational Circuits Issues in Dynamic Design 1: Charge Leakage CLK Clk Mp Out CL A Clk Evaluate VOut Me Precharge Leakage sources Dominant component is subthreshold current EE141 Integrated © Digital Circuits2nd 80 Combinational Circuits Solution to Charge Leakage Keeper Clk Mp A Mkp CL Out B Clk Me Same approach as level restorer for pass-transistor logic EE141 Integrated © Digital Circuits2nd 81 Combinational Circuits Issues in Dynamic Design 2: Charge Sharing Clk Mp Out A CL B=0 Clk Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness CA Me EE141 Integrated © Digital CB Circuits2nd 82 Combinational Circuits Charge Sharing Example Clk A A B B B Cc=15fF C C Ca=15fF Out CL=50fF !B Cb=15fF Cd=10fF Clk EE141 Integrated © Digital Circuits2nd 83 Combinational Circuits Charge Sharing VDD case 1) if V out < VTn VDD Clk Mp Mp Out Out CL A A = BB 00 Clk CL Ma Ma XX M Mb b Mee M EE141 Integrated © Digital a CC a CC bb Circuits2nd C L VDD = C L Vout t + Ca VDD – V Tn V X or Ca V out = Vout t – V DD = – -------- V DD – V Tn V X C L case 2) if V out > VTn C --------------------a - Vout = –V DD C + C a L 84 Combinational Circuits Solution to Charge Redistribution Clk Mp Mkp Clk Out A B Clk Me Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power) EE141 Integrated © Digital Circuits2nd 85 Combinational Circuits Issues in Dynamic Design 4: Clock Feedthrough Clk Mp A Out CL B Clk Me EE141 Integrated © Digital Circuits2nd Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out. 88 Combinational Circuits Clock Feedthrough Clock feedthrough Clk Out 2.5 In1 1.5 In2 In3 In & Clk 0.5 In4 Out Clk -0.5 0 0.5 Time, ns 1 Clock feedthrough EE141 Integrated © Digital Circuits2nd 89 Combinational Circuits Other Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce) EE141 Integrated © Digital Circuits2nd 90 Combinational Circuits Cascading Dynamic Gates V Clk Clk Mp Mp Out1 Clk Me Out2 In In Clk Clk Me Out1 VTn V Out2 t Only 0 1 transitions allowed at inputs! EE141 Integrated © Digital Circuits2nd 91 Combinational Circuits Domino Logic Clk In1 In2 In3 Clk EE141 Integrated © Digital Mp 11 10 PDN Me Circuits2nd Out1 Clk Mp Mkp Out2 00 01 In4 In5 Clk PDN Me 92 Combinational Circuits Why Domino? Clk Ini Inj Clk PDN Ini Inj PDN Ini Inj PDN Ini Inj PDN Like falling dominos! EE141 Integrated © Digital Circuits2nd 93 Combinational Circuits Properties of Domino Logic Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition Input capacitance reduced – smaller logical effort EE141 Integrated © Digital Circuits2nd 94 Combinational Circuits Designing with Domino Logic VDD VDD VDD Clk Mp Clk Mp Out1 Mr Out2 In1 In2 In3 PDN PDN In4 Can be eliminated! Clk Me Clk Me Inputs = 0 during precharge EE141 Integrated © Digital Circuits2nd 95 Combinational Circuits Footless Domino VDD Clk VDD Mp Clk Mp Out1 0 Clk 1 0 Outn 1 0 In2 0 Mp Out2 In1 1 VDD 1 0 In3 1 0 1 Inn 1 0 The first gate in the chain needs a foot switch Precharge is rippling – short-circuit current A solution is to delay the clock for each stage EE141 Integrated © Digital Circuits2nd 96 Combinational Circuits Differential (Dual Rail) Domino off Mp Mkp Clk Out = AB 1 on Mkp 0 Clk Mp 1 A !A 0 Out = AB !B B Clk Me Solves the problem of non-inverting logic EE141 Integrated © Digital Circuits2nd 97 Combinational Circuits np-CMOS Clk In1 In2 In3 Mp 11 10 PDN Clk Me Out1 Clk Me In4 In5 PUN 00 01 Clk Mp Out2 (to PDN) Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN EE141 Integrated © Digital Circuits2nd 98 Combinational Circuits NORA Logic Clk In1 In2 In3 Mp 11 10 Out1 PDN Clk In4 In5 PUN Clk to other PDN’s WARNING: Very sensitive to noise! EE141 Integrated © Digital Me 00 01 Me Circuits2nd Clk Mp Out2 (to PDN) to other PUN’s 99 Combinational Circuits