Sedra: Chapter 14 (Output stages and Power Amplifiers)

Report
Output Stages and Power
Amplifiers
1
Figure 14.1 Collector current waveforms for transistors operating in (a) class A, (b) class B,
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Figure 14.1 (Continued) (c) class AB, and (d) class C amplifier stages.
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Figure 14.2 An emitter follower (Q1) biased with a constant current I supplied by transistor Q2.
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Figure 14.3 Transfer characteristic of the emitter follower in Fig. 14.2. This linear characteristic is obtained by neglecting the change in vBE1
with iL. The maximum positive output is determined by the saturation of Q1. In the negative direction, the limit of the linear region is
determined either by Q1 turning off or by Q2 saturating, depending on the values of I and RL.
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Figure 14.4 Maximum signal waveforms in the class A output stage of Fig. 14.2 under the condition I = VCC /RL or, equivalently, RL = VCC /I.
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Figure 14.5 A class B output stage.
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Figure 14.6 Transfer characteristic for the class B output stage in Fig. 14.5.
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Figure 14.7 Illustrating how the dead band in the class B transfer characteristic results in crossover distortion.
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Figure 14.8 Power dissipation of the class B output stage versus amplitude of the output sinusoid.
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Figure 14.9 Class B circuit with an op amp connected in a negative-feedback loop to reduce crossover distortion.
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Figure 14.10 Class B output stage operated with a single power supply.
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Figure 14.11 Class AB output stage. A bias voltage VBB is applied between the bases of QN and QP, giving rise to a bias current IQ given by Eq.
(14.23). Thus, for small vI, both transistors conduct and crossover distortion is almost completely eliminated.
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Figure 14.12 Transfer characteristic of the class AB stage in Fig. 14.11.
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Figure 14.13 Determining the small-signal output resistance of the class AB circuit of Fig. 14.11.
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Figure 14.14 A class AB output stage utilizing diodes for biasing. If the junction area of the output devices, QN and QP, is n times that of the biasing
devices D1 and D2, and a quiescent current IQ = nIBIAS flows in the output devices.
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Figure 14.15 A class AB output stage utilizing a VBE multiplier for biasing.
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Figure 14.16 A discrete-circuit class AB output stage with a potentiometer used in the VBE multiplier. The potentiometer is adjusted to yield the desired
value of quiescent current in QN and QP.
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Figure 14.17 Electrical equivalent circuit of the thermal-conduction process; TJ – TA = PDqJA.
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Figure 14.18 Maximum allowable power dissipation versus ambient temperature for a BJT operated in free air. This is known as a “power-derating”
curve.
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Figure 14.19 The popular TO3 package for power transistors. The case is metal with a diameter of about 2.2 cm; the outside dimension of the “seating
plane” is about 4 cm. The seating plane has two holes for screws to bolt it to a heat sink. The collector is electrically connected to the case. Therefore an
electrically insulating but thermally conducting spacer is used between the transistor case and the “heat sink.”
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Figure 14.20 Electrical analog of the thermal conduction process when a heat sink is utilized.
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Figure 14.21 Maximum allowable power dissipation versus transistor-case temperature.
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Figure 14.22 Thermal equivalent circuit for Example 14.5.
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Figure 14.23 Safe operating area (SOA) of a BJT.
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Figure 14.24 A class AB output stage with an input buffer. In addition to providing a high input resistance, the buffer transistors Q1 and Q2 bias the
output transistors Q3 and Q4.
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Figure 14.25 The Darlington configuration.
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Figure 14.26 The compound-pnp configuration.
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Figure 14.27 A class AB output stage utilizing a Darlington npn and a compound pnp. Biasing is obtained using a VBE multiplier.
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Figure 14.28 A class AB output stage with short-circuit protection. The protection circuit shown operates in the event of an output short circuit while
vO is positive.
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Figure 14.29 Thermal-shutdown circuit.
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Figure 14.30 The simplified internal circuit of the LM380 IC power amplifier. (Courtesy National Semiconductor Corporation.)
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Figure 14.31 Small-signal analysis of the circuit in Fig. 14.30. The circled numbers indicate the order of the analysis steps.
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Figure 14.32 Power dissipation (PD) versus output power (PL) for the LM380 with RL = 8 W. (Courtesy National Semiconductor Corporation.)
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Figure 14.33 Structure of a power op amp. The circuit consists of an op amp followed by a class AB buffer similar to that discussed in Section 14.7.1.
The output current capability of the buffer, consisting of Q1, Q2, Q3, and Q4, is further boosted by Q5 and Q6.
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Figure 14.34 The bridge amplifier configuration.
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Figure 14.35 Double-diffused vertical MOS transistor (DMOS).
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Figure 14.36 Typical iD–vGS characteristic for a power MOSFET.
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Figure 14.37 The iD–vGS characteristic curve of a power MOS transistor (IRF 630, Siliconix) at case temperatures of –55C, +25C, and +125C.
(Courtesy Siliconix Inc.)
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Figure 14.38 A class AB amplifier with MOS output transistors and BJT drivers. Resistor R3 is adjusted to provide temperature compensation
while R1 is adjusted to yield the desired value of quiescent current in the output transistors. Resistors RG are used to suppress parasitic
oscillations at high frequencies. Typically, RG = 100 W.
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Figure 14.39 Capture schematic of the class B output stage in Example 14.6.
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Figure 14.40 Several waveforms associated with the class B output stage (shown in Fig. 14.39) when excited by a 17.9-V, 1-kHz sinusoidal signal.
The upper graph displays the voltage across the load resistance, the middle graph displays the load current, and the lower graph displays the
instantaneous and average power dissipated by the load.
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Figure 14.41 The voltage (upper graph), current (middle graph), and instantaneous and average power (bottom graph) supplied by the positive voltage
supply (+VCC) in the circuit of Fig. 14.39.
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Figure 14.42 Waveforms of the voltage across, the current through, and the power dissipated in the pnp transistor QP of the output stage shown in Fig.
14.39.
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Figure 14.43 Transfer characteristic of the class B output stage of Fig. 14.39.
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Figure 14.44 Fourier-series components of the output waveform of the class B output stage in Fig. 14.39.
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Figure P14.8
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Figure P14.11
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Figure P14.22
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Figure P14.37
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Figure P14.38
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Figure P14.42
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Figure P14.50
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Figure P14.52
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