ECE369: Fundamentals of Computer Architecture

Report
ECE 369
Chapter 4
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addi $29, $29, 16
Assume register $29 initially contains the number 129.
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addi $29, $29, 16
Assume register $29 initially contains the number 129.
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What happens at stuck at 0 for….?
RegWrite
R-format instructions, in addition to lw: will not be able to write
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their results to the register file.
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What happens at stuck at 0 for….?
ALUop1
All R-format instructions
How about add or sub?
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What happens at stuck at 0 for….?
ALUop0
Beq instruction will not work because the ALU will perform
addition instead of subtraction
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What happens at stuck at 1 for….?
RegWrite
Sw (beq) will overwrite a random register with either the store
address (branch target) or random data from the memory data read7
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New inruction (l_inc)=
lw
$rs,
addi $rt,
($rt)
$rt,1
You can modify the datapath:
a) Introduce new module(s)
b) Introduce input(s)/output(s)
to existing modules
c) Add new control signal(s)
Reg
Dest
ALU
Src
MEMto
Reg
Reg
Write
Mem
Read
Mem
Write
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Branch
ALUop1
ALUop0
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New instruction (l_inc)= lw
$rs,
addi $rt,
($rt)
$rt,1
Auto incrementer unit
Second write port (WriteData2)
Write2 control signal
Feed Inst[25-21] to second write port
Write2 controls this write
Reg
Dest
ALU
Src
MEMto
Reg
Reg
Write
Mem
Read
0
1
1
1
1
Mem
Write
Branch
ALU
Op1,op0
Write2
0
0
00
1
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Modify single cycle to implement Jump Register
(Jr $rs) =
PC<-$rs
Reg
Dest
ALU
Src
MEMto
Reg
Reg
Write
Mem
Read
Mem
Write
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Branch
ALU
Op1,op0
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Modify single cycle to implement Jump Register
(Jr $rs) =
PC<-$rs
Reg
Dest
ALU
Src
MEMto
Reg
Reg
Write
Mem
Read
x
x
x
0
x
Mem
Write
Branch
ALU
Op1,op0
Jump
Reg
0
0
x
1
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bmez $rt, $rs, imm16
RegWrite
reads the value of memory in address (R[$rs] + R[$rt]), compares it
to zero and if zero then branches to the zero extended immediate,
otherwise it goes on to the next instruction.
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sw+ is a “store word, with post increment”
M[R[rs]] = R[rt]
R[rs] = R[rs] + imm
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Modify the datapath to handle:
lw rt, rs
# R[rt] = M[R[rs]]
sw rt, rs
# M[R[rs]] = R[rt]
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mov rs, rd
# R[rd] = R[rs];
Instr
ALUsrc1
ALUsrc2
ALUsrc3
ALUop1
ALUop2
MemRead
MemWrite
RegWrite
mov
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a_new
rd, rs, rt, imm
# Memory[R[rs]]= (R[rs] | imm) + R[rt]
Instr
ALUsrc1
ALUsrc2
ALUsrc3
ALUop1
ALUop2
MemRead
MemWrite
RegWrite
a_new
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b_new
rd,rs,rt,imm
# R[rd]=R[rs]+Imm+ Memory[R[rs]]
Instr
ALUsrc1
ALUsrc2
ALUsrc3
ALUop1
ALUop2
MemRead
MemWrite
RegWrite
b_new
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Timing Analysis
Func. Unit
Instruction Memory (Read)
Data Memory (Read/Write)
Add
ALU
Register (Read)
Register (Write)
Latency
2ns
5ns
1ns
3ns
2ns
4ns
Given the latencies above, what is the minimum
cycle time for this processor based on the
addi_lw , mov, a_new and b_new instructions?
Show your work to get credit.
Instruction
Instruction
Memory
Add
Potential resources used by an instruction
Register Register Data
Data
Read
Write
Memory
Memory
Read
Write
Total
ALU1
ALU2
mov
a_new
b_new
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Mov: Rt=0, imm=0
a_new: ALU2 output needs to be connected to write data part
through a mux
Instr
ALUsrc1
ALUsrc2
ALUsrc3
ALUop1
ALUop2
MemRead
MemWrite
RegWrite
mov
x
1
1
add
add
0
0
1
a_new
b_new 1
0
0
add
add
1
0
1
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Func. Unit
Instruction Memory (Read)
Data Memory (Read/Write)
Add
ALU
Register (Read)
Register (Write)
Latency
2ns
5ns
1ns
3ns
2ns
4ns
Given the latencies what is the minimum cycle
time for this processor based on the addi_lw ,
mov, a_new and b_new instructions? Show your
work to get credit.
Instruction
Instruction
Memory
Add
addi_lw
mov
a_new
b_new
2
2
2
2
1
1
1
1
Potential resources used by an instruction
Register Register Data
Data
Read
Write
Memory Memory
Read
Write
2
2
2
2
4
4
0
4
0
0
0
0
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0
5
5
Total
ALU1
ALU2
3
3
3
3
3
3
3
3
14
14
15
16
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