### Golden Rules for Low Emission

```Design guidelines for
EMC of Components
Summary
1.
Which problems?
2.
EMC Guidelines at PCB level
3.
IC Guidelines for low emission
4.
IC Guidelines for low immunity
5.
Starcore case study
2
April 15
EMC management
EMC should be taken into account at early design stage…
design and layout for EMC
3
April 15
EMC guidelines
Power integrity
(PI)
Signal integrity
(SI)
ESD, EFT,
EOS
immunity (RI)
Conducted
emission (CE)
Integrated circuits /
electronic applications
emission (RE)
Conducted
immunity (CI)
4
April 15
EMC guidelines at PCB level
Signal integrity (SI) issue

Example: voltage measurement at 3 terminals of two 20 cm long
parallel PCB tracks.

The first line is excited by a pulse generator, the second is
Origin of effects
on both lines ?
EMC guidelines at PCB level
Signal integrity (SI) issue

Let’s consider a transmission along two conductors = 2-conductor
transmission line. Let’s suppose an homogeneous lossless line

Equivalent model:
ZG
Interconnect
L
z
I(z,t)
++++++
l
ZC 
- - - - - - -c
VG
Thevenin
generator

0
The voltage and current on each point
of the line is superposition of a
forward and backward voltage,
travelling in opposite directions.
6
ZL
I(z,t)
Transmission line
 z
 z
V z, t   V   t    V   t  
 v
 v
1  z  1  z 
I z, t  
V t   
V t  
ZC  v  ZC  v 
1
1
v

lc

EMC guidelines at PCB level
Signal integrity (SI) issue

The voltage at each point of the line depends on the reflection coefficient at
each line terminals:
 L
V t  
v  Z L  ZC
L  

L

 Z L  ZC
V  t  
 v

V  t  ZG  ZC
G   
V t  ZG  ZC
Transient behavior of voltage at each line terminals:
At generator side (input):
At generator side (input):
V z  0, t   V  t   V  t   V  0, t  1  G 
 L
 L
V z  L, t   V   t    V   t    V  L, t  1  L 
 v
 v
Complex transient behavior related to the
reflection coefficient on each extremities
and transmission line discontinuities
7
April 15
EMC guidelines at PCB level
Signal integrity (SI) issue

Analysis of the round-trip period of the wave along the line
Source G
Time (ns)
0
ZC
V 0, t   V 0, t   V0 
VG
ZG  ZC
L/v

2L/v
V0

VL(0)=0V
V1  V0L  1.44V
VL  V0 1  L 
V 0, t   V0  V1 1  G 
V 0, t   V0 1  L 1  G 
Vsource
V0 1  L 
V 1  L 1  G 

0
V0
Overshoot /
Undershoot

Overshoot /
Undershoot
0
2L/v
4L/v
t
0
8
L/v
April 15
3L/v
t
EMC guidelines at PCB level
Signal integrity (SI) issue
Zc ; Tp
VL
VG
VL or VG
Vdd
Criterion for SI issue:
Overshoot
VIH
Undetermined
level
Undershoot
VIL
0
Ringing
t
if Tr is the rising or falling time of
a signal, SI issues due to the
propagation of the EM wave along
the transmission line arise if:
Tr  TP
Longer setting
time
9
April 15
EMC guidelines at PCB level
Signal integrity (SI) issue
design and layout for EMC
10
April 15
EMC guidelines at PCB level
Ensuring Signal integrity – Rule 1
Cancel reflection coefficient at each line terminals by
impedance matching
L  0  Z L  ZC
Impedance matching of a
uniform transmission line with
constant characteristic
impedance Zc.
G  0  ZG  ZC

Vcc
Practical designs for a digital transmission:
Zc
Rs
Zc
Rpd
Rpd
Ct
Rs : serial resistor= Rdriver - Zc
Rpd : pull down resistor = Zc
11
April 15
EMC guidelines at PCB level
Ensuring Signal integrity – Rule 2
Control the characteristic impedance of (2-conductor) transmission line
(PCB track, package)  avoid line discontinuities

Microstrip line configuration:
W
t
εr
I
Z C  
h
Ideal ground plane
87
 5.98h 
ln

0
.
8
W

t
 eff  1.414 

Tp  ps / mm  3.34 0.475 r  0.67
Is it better to use wide or narrow trace ?
12
April 15
EMC guidelines at PCB level
Ensuring Signal integrity – Rule 3
Ensure a controlled and short return current path.

Place a full ground plane in microstrip line.

Avoid slot in return plane (e.g. ground plane)

Keep a symmetry (avoid unbalance in the return current path)
CORRECT
Microstrip line
Ground plane
Microstrip line
I
Return
current
Low frequency behavior
Microstrip line
Ground plane
with a slot
I
Ground plane
Return
current
I
Return
current
High frequency behavior
13
April 15
EMC guidelines at PCB level
Ensuring Signal integrity – Rule 3

Example: a microstrip line routed over 2 separated power planes.
SI design rule
violation
14
April 15
EMC guidelines at PCB level
Signal integrity (SI) - Crosstalk

Let’s consider 2 traces separated by a distance d.
Trace 1 (emitter)
I1
d
Trace 2 (victim)
W
W I1’
I2
h V

Crosstalk (near-field
coupling)
εr
Parasitic return
current path
“Normal” return
current path
Equivalent model:
Capacitive
coupling
VE
RS
RNE
RL
Emitter trace
CM
LM
RFE
Far end
Victim trace
Near end
VNE
15
Inductive
coupling
VFE
April 15
EMC guidelines at PCB level
Signal integrity (SI) - Crosstalk

Low frequency model (quasi-static approximation  propagation effects
neglected)
VNE
RNE  RL RFECM  LM 
 j
RFE  RNE  RL  RS 
VS
VNE or VFE dBV
RFE  RL RNE CM  LM 
VFE
 j
RFE  RNE  RL  RS 
VS
VNE
VFE
f
Validity of quasi-static
approximation
16
April 15
EMC guidelines at PCB level
Ensuring Signal integrity – Rule 4
Increase the isolation between emitter and victim lines

Increase the distance between traces (rule 3 W = “the separation between
traces must be 3 times the width of the trace as measured from centerline
to centerline of two adjacent traces”)
W
< 3W
W
t
h
(εr = 4.5)
Substrate
ground
17
April 15
EMC guidelines at PCB level
Power integrity (PI) issue – Power Distribution Network
Bulk capacitor
(Low frequency)
Power
source
Ground
reference
HF
capacitor
(ceramic)
Ferrite
Voltage
converter /
regulator 1 µF – 10 mF
100 nF – 1 nF
PCB – Power /
ground plane
Vdd
Vss
1 nF
Transistors, gates,
interconnects
18
April 15
Package
and IC
EMC guidelines at PCB level
Power integrity (PI) issue
Power supply source
(regulator, DC-DC converter)
ΔVdd
PDN
Vdd
i(t)
Noisy Integrated
circuit
PDN
Vss
Circuit
Power supply
bounce
V  RPDN i  LPDN
19
i
t
Delta-I noise
April 15
ΔVss
EMC guidelines at PCB level
Power integrity (PI) issue

Example: on-chip measurement of the power supply voltage fluctuation
of a digital circuit
Low frequency
contribution
High frequency
contribution
Switching
Switching
Switching
Noise with a large frequency content and
some major resonance modes
20
April 15
EMC guidelines at PCB level
Power integrity (PI) issue

Equivalent model of a PDN (the most basic model…)
PDN
Circuit
Vdd
ZPDN
ΔVdd
Power supply voltage bounce:
Vdd  f   Z PDN  f   I IC  f 
IIC
gnd
 Ensuring power integrity relies on the control of a low impedance of the PDN.

A target impedance ZT can be defined as a design objective:
ZT 
Vdd max
I average
ZPDN
Zt
Frequency
Target frequency range
21
April 15
EMC guidelines at PCB level
Ensuring Power integrity – Rule 1
Reduce interconnect parasitic (mainly inductance) of power and ground
connections

Use traces as wide as possible for Vdd and Vss connections

i.e. use power and ground planes

Be careful of the common impedance of Vdd and Vss connections (finite
impedance, even for ground plane):
Single point grounding with
serial circuits
Régulateur
VDD
L1
Circuit 1
VSS
VDD
Circuit 2
Direct grounding to a
reference ground plane
VDD
Circuit 3
VDD
Régulateur
L2
VSS
L3
Circuit 1
VDD
Circuit 2
V1  L1
dI 1  dI 2  dI 3
dt
V2  V1  L2
I2+ I3
dI 2  dI 3
dt
I3
V3  V2  L3
Circuit 3
VSS
L1
Plan de masse
dI 3
dt
22
April 15
I1
VSS
VSS
VSS
I1+I2+ I3
VDD
L2
I2
L3
I3
EMC guidelines at PCB level
Ensuring Power integrity – Rule 2
Add decoupling capacitor to reduce power supply bounce as
close as possible from noise source (current demand)

Principle:
Voltage
regulator
Local charge
tank
Voltage
bounce v(t)
Decoupling
capacitor
IC
Vdd
Vss
Vdd
PCB
Vss
In time domain
i t   Cdec
i(t)
In frequency domain
dv t 
dt
V  f   ZCdec I  f 
Large capacitors reduce
PDN impedance.
Large capacitors react
rapidly to charge demand.
23
April 15
EMC guidelines at PCB level
Ensuring Power integrity – Rule 2
mΩ,

Effect of on-board capacitors:
No
decoupling
X7R 50 V ceramic capacitors
Customer’s
specification
Parasitic emission
(dBµV)
100 µF electrolytic capacitor
80
70
60
50
40
30
20
10-100 nF
10
0 decoupling
-10
1
24
10 – 15 dB
Efficient on
10
100
Frequency (MHz)
April 15
1000
EMC guidelines at PCB level
Ensuring Power integrity – How choosing decoupling capacitor

If ideal capacitor, only one decoupling capacitor would be enough:
I  tr
Cdec 
Vdd max
• Cdec: the minimum capacitor able to provide a current to
the circuit without any large voltage fluctuations.
• ΔVddmax : max allowed voltage fluctuation
• ΔI : current peak absorbed by the circuit
• tr : rise time of the current peak

However, due to the parasitic elements associated to decoupling
capacitors, its efficiency frequency range is limited or it can not respond
to rapid current demand.

It is necessary to place several decoupling capacitors in parallel to
increase the efficiency frequency range of the decoupling.
25
April 15
EMC guidelines at PCB level
Ensuring Power integrity – How choosing decoupling capacitor

Methodology to optimize the choice of decoupling capacitors:
Board model
Regulator model
Circuit(s) model
Define Zt
PDN without decoupling model
Define freq. range of decoupling
Fmin  Fmax
Compute ZPDN
YES
If ZPDN(f) > Zt for f in [Fmin;Fmax]
NO
capa values
Power integrity OK – Decoupling
budget
Capacitors model
April 15
EMC guidelines at PCB level
Ensuring Power integrity – How choosing decoupling capacitor

Example: decoupling of a 16 bit microcontroller (dspic33F).

The circuit produces a significant amount of noise over the range 1 – 500 MHz.

We select Zt = 2 Ω.
IC Current (1 Ω probe)
Z PDN (VNA measurement)
Board + IC without decap
ZT
With 6×100 nF
decap
27
April 15
EMC guidelines at PCB level
Ensuring Power integrity – Anti-resonance issue

What happens if 2 “real” capacitors are placed in parallel ?
Fantires
Fantires =
28
April 15
EMC guidelines at PCB level
Ensuring Power integrity – Anti-resonance issue

Example: power integrity of a 16 bit microcontroller (dspic33F) with 6×100 nF
X7R decoupling capacitor.

The PDN impedance measurement shows an anti-resonance at 162 MHz
PDN equivalent model
Fantires
What is the cause of this anti-resonance ?
29
April 15
EMC guidelines at PCB level
Ensuring Power integrity – Anti-resonance issue

Example: power integrity of a 16 bit microcontroller (dspic33F) with 6×100 nF
X7R decoupling capacitor.

Measurement of power supply voltage in time domain (16 I/O pads switch
simultaneously).
30
April 15
EMC guidelines at PCB level
Ensuring Immunity – Anti-resonance issue

Example: power integrity of a 16 bit microcontroller (dspic33F) with 6×100 nF
X7R decoupling capacitor.

Measurement of conducted immunity (harmonic signal coupled on power
supply plane according to DPI standard). At each harmonic frequency, the
disturbance power is increased until a circuit failure arises.
Max. Power
31
EMC guidelines at PCB level

Radiated emissions come from interconnects excited by a transient
current or voltage. They become parasitic antennas.

 Dipole antenna (electric)
 Loop antenna (magnetic)
 Low impedance load (power supply, I/O
 H field proportional to surface S
Magnetic
field
Circuit
VSS
high impedance)
 E field proportional to length l
Electric field
Circuit
I
Clock
VDD
Length l
Surface S
32
April 15
EMC guidelines at PCB level


Common mode appears when the return current path is not perfectly defined.
If I1 ≠ I2
Interco 1
Differential
mode
I1
I2
Decomposition in 2
distinct propagation
modes
Id
1
Id
2
Ic
Interco 2
ID 
I1  I 2
I1  I D  I C
2
IC 
I1  I 2 I 2  I C  I D
2
Common
mode
1
2
33
April 15
Ic
EMC guidelines at PCB level

Comparison of common and differential radiated mode.

Let’s consider electrically 2 short parallel interconnects (length L << λ):
ED max  1.316.1014
EC
max
 1.257 .10
L=10 cm, d=2 mm, r = 1 m,
ID = 50 mA, IC = 5 mA
L.d . f 2
ID
r
6
L. f
IC
r
 L: interconnect length
 d: interconnect separation
 f: frequency of excitation current
 r: distance between E field measurement
point and interconnect centers
 ID and IC: differential and common mode
currents
 ED and EC: differential and common
34
April 15
EMC guidelines at PCB level
Reducing radiated emission – Rule 1
Reduce parasitic antenna (length or surface) to reduce differntial and

Identify current loops on PCB and reduce their surface.

Place decoupling capacitors as close as possible to IC pins.

Use power or ground plane to reduce current loop surface.

Reduce the length of interconnects which carry high frequency signals.
Circuit
Circuit
VDD
VSS
Id
VDD
Decoupling
capacitor
VSS
Id
Smaller loop  Reduced
Large loop  High
35
April 15
Decoupling
capacitor
EMC guidelines at PCB level
Reducing radiated emission – Rule 2
Control the current return path to reduce common mode
Example 2: one differential
output buffer with a non
symmetrical routing
Example 1: one Vdd pin but
two Vss pins
IVdd = IVSS1+IVSS2
Power
Circuit
VSS2
VDD
VSS1
Differential buffer
IVdd
D-
IVss1
IVSS2
I+
D+
GND
Ic
36
April 15
I-
I+ ≠ IParasitic
coupling
EMC guidelines at PCB level
Reducing radiated emission – Rule 3
Use a “good” ground plane(s) to shield noisy interconnects

Use coplanar or stripline configuration to shield noisy interconnect.

A “good” reference plane is equipotential at any point !

Connect two reference plane witth same potential by vias regular interval
less than λ/20 !
Correct connection
between two planes with
same potential
Stripline configuration
Ref plane
line
GND
d

20
via
Ref plane
GND
37
April 15
EMC guidelines at PCB level

Basic digital applications routed on a 2 layer board with the auto-router
function of the board design tool. Only one 100 nF decoupling capacitor
for all the application.

Measurement of radiated emission in TEM cell.
Limit CISPR25
38
EMC guidelines at PCB level

Numerous EMC design rules violation: large power-ground loops, long
fast clock interconnect, return path not ensured by a ground plane…

Change the placement & routing of the board by starting to place Vdd/Vss
and fast clock, add a ground plane on both side.

Design rule violation examples:
Large loop
CMOS
inverter
Vdd
connection
Vss
connection
39
“High speed”
clock source
Equivalent surface of
fast clock interconnect
EMC guidelines at PCB level
Top layer
Effect of placement & Routing improvement
(still one 100 nF decoupling capacitor)
-30 dB
Bottom layer
40
April 15
EMC guidelines at PCB level
Effect of decoupling capacitors
(one capacitor per circuit)
Effect of GND vias density
+ or – effect
depending on freq.
≈ -5 dB
41
April 15
EMC guidelines at PCB level
Summary
 EMC can be improved at PCB level, mainly by an adequate
placement and routing of rapid signals, power and ground
references.
 Several EMC issues have the same root causes  one EMC
design rule can solve several problems.
 The modeling is important to understand the problem and
optimize solution.
 An accurate IC model is mandatory to manage EMC at PCB
level.
42
April 15
Golden Rules for Low Emission
Rule 1: Power supply routing strategy
A) Use shortest interconnection to reduce the serial inductance
•
•
•
Inductance is a major source of resonance
Each conductor acts as an inductance
Ground plane modifies inductance value (worst case is far from ground)
Reducing inductance
decreases SSN !!
Bonding: L=1nH/mm
43
April 15
Golden Rules for Low Emission
Rule 1: Power supply routing strategy
A) Use shortest interconnection to reduce the serial inductance
L up to 10nH
Die of the IC
Long
bonding
Far from ground
PCB
Short
Flip chip package:
L up to 3nH
Die of the IC
balls
Close from ground
Requirements for high speed microprocessors : L < 50 pH !
44
April 15
Golden Rules for Low Emission
Rule 1: Power supply routing strategy
B) Place enough supply pairs: Use One pair (VDD/VSS) for 10 IOs
9 I/O ports
Fail
Correct
45
April 15
Golden Rules for Low Emission
Rule 1: Power supply routing strategy
C) Place supply pairs close to noisy blocks
Current density simulation
Layout view
Memory
PLL
Digital core
VDD / VSS
VDD / VSS
VDD / VSS
46
April 15
Golden Rules for Low Emission
Rule 1: Power supply routing strategy
D) Place VSS and VDD pins as close as possible
EM field
• to increase decoupling capacitance that reduces fluctuations
• to reduce current loops that provoke magnetic field
contributions
current
Reduced
contributions
EM wave
EM wave
current
Die
Current
loop
currents
47
April 15
Golden Rules for Low Emission
Rule 1: Power supply routing strategy
Case study 2:
Case 1 : Infineon Tricore
Case 2 : virtex II
Worst case
not enough supply pairs,
Not ideal
Not enough supply for IOs :
(core emission is lower than IO one)
48
April 15
Golden Rules for Low Emission
Rule 1: Power supply routing strategy
Case study 2:
2 FPGA , same power supply, same IO drive, same characteristics
Supply strategy very different !
• More Supply pairs for IOs
• Better distribution
courtesy of Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.com
49
April 15
Golden Rules for Low Emission
Rule 1: Power supply routing strategy
Case 1: low emission due to
a large number of supply
pairs well distributed
Case 2: higher emission
level (5 times higher)
courtesy of Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.com
50
April 15
Golden Rules for Low Emission
Rule 1: Power supply routing strategy
Case study 3: conducted (150 ohms probe placed on Vdd)
and radiated (TEM cell) emission from a microcontroller
mounted in either & 208-BGA or a 324-BGA.
208-BGA (31
Vdd/Vss pairs)
324-BGA (49
Vdd/Vss pairs)

Larger conducted emission from 208-BGA
(less power supply pins)

(larger interconnects)
E. Rogard and al., "Characterization and Modelling of Parasitic Emission of
a 32-bit Automotive Microcontroller Mounted on 2 Types of BGA", IEEE
EMC Symposium Austin, Texas, USA 2009
51
April 15
Golden Rules for Low Emission
On chip decoupling capacitance versus technology and complexity:
Intrinsic on-chip supply
capacitance
65nm
100nF
90nm
0.18µm
10nF
0.35µm
1.0nF
100pF
Devices on
chip
10pF
100K
1M
10M
100M
1G
Example: in 65nm technology, for a 200 Million devices on chip the intrinsic capacitance is 10nF
52
April 15
Golden Rules for Low Emission

Effect of on chip capacitance: smooth on-chip voltage fluctuation and reduce conducted
emission.

Example: two versions of a CMOS 90 nm digital core, Vdd = 1.2 V, same mounting board:

Core 1: No on-chip decoupling capacitance

Core 2 : Add 100 pF MIM decoupling capacitance
1 ohm conducted measurement
On-chip voltage measurement
59 mV
27 mV
53
April 15
A. Boyer (LAAS-CNRS)
Golden Rules for Low Emission
Rule 3: Reduce I/O noise
 Reduction of the fast rate of I/O current.

Minimize the number of simultaneous switching lines (bus coding)

Reduce di/dt of I/O by controlling slew rate and drive
Tr1
Tr2
SR & Drive
control
Emission
level
1/Tr2
54
f
1/Tr1
April 15
Golden Rules for Low Emission
Rule 3: Reduce I/O noise
 Example: I/O buffer with Drive and slew rate control options: Full or
reduced drive, high and limited slew rate.

Impact of I/O options on timing waveform:
Rise time = 2 ns
Rise time = 8.6 ns
Full Drive – High slew rate
Reduced Drive – High slew rate
55
April 15
Golden Rules for Low Emission
Rule 3: Reduce I/O noise
 Impact of I/O options on timing waveform and output drive current:
What is the more « emissive » option ? The less emissive ?
56
April 15
Golden Rules for Low Emission
Rule 3: Reduce I/O noise
 Comparison of conducted emission (1 ohm method)
57
Golden Rules for Low Emission
Rule 3: Reduce I/O noise
 Comparison of conducted emission (1 ohm method)
58
April 15
Origin of electromagnetic emission
Rule 4: Reduce SSN
 The switching of output buffer contributes to a large part of conducted and
radiated emission. When several I/O switches simultaneously, their contributions
tend to add: Simultaneous Switching Noise.
Minimize the number of simultaneous switching lines (bus coding)
Effect of the number of
16 output buffers, two different
simultaneous switching buffers
switching sequences.

59
April 15
Golden Rules for Low Emission
Rule 5: Reduce clock noise – Spread Spectrum Frequency Modulation

Reduction or spreading of clock harmonics by frequency modulation.

Example : sinus clock at Fc = 100 MHz vs modulated sinus clock:
Reduction of narrow
band RF energy
Carrier frequency Fc = 100 MHz
Modulation frequency FM = 1 MHz
Frequency excursion dF = +/- 5 MHz
 Modulation index md = 5


df
S FM t   cos C t 
cosM t 
FM


S FM t   cosC t  m d cos M t 
Carson rule:
B  2  Fmod  md  1
60
April 15
Golden Rules for Low Emission
Rule 5: Reduce clock noise – Spread Spectrum Frequency Modulation
 In practice, a triangular signal is used as modulating signal.
Freq. modulation ΔF
Clock in
Clock out
Tc
Modulant
Tc+/-dt
Frequency Modulated clock
+/- dt
t
TMod
dP
Modulated
clock
Carson rule applies also:
B  2  Fmod  md  1
If Fmod < RBW (reso BW of the
B
Unmodulated
clock
61
 B 
dPdB  10log

 RBW 
Golden Rules for Low Emission
Rule 5: Reduce clock noise – Spread Spectrum Frequency Modulation

Real case study: FM-PLL block of the 32 bit microcontroller MPC 5604B from
Freescale. PLL frequency set at 64 MHz.

Measurement of near-field emission above the circuit.

Modulation parameters: triangular waveform, FM = 100 KHz, dF = +/- 0.64 MHz.

10 dB
Predicted value of
A. Boyer (LAAS-CNRS)
62
April 15
Golden Rules for Low Emission
Rule 5: Reduce clock noise – Spread Spectrum Frequency Modulation

Real case study: Effect on emission spectrum

Modulation parameters: triangular waveform, FM = 100 KHz, dF = +/- 0.64 MHz.

Average reduction of 64 MHz
harmonics = 10.6 dB
A. Boyer (LAAS-CNRS)
63
April 15
Golden Rules for Low Emission
Rule 5: Reduce clock noise – Spread Spectrum Frequency Modulation

The reduction amount is dependent of the receiver bandwidth RBW if the
modulation frequency is less than RBW.

Example: FM = 50 KHz, dF = +/- 1.28 MHz.

RBW = 1 KHz vs. RBW = 100 KHz.
3 dB
A. Boyer (LAAS-CNRS)
64
April 15
Golden Rules for Low susceptibility
Rule 1: Decoupling capacitance is also good for immunity
Immunity level
(dBm)
Decoupling
capacitance
• DPI aggression of a digital core
• Reuse of low emission design rules
for susceptibility
• Efficiency of on-chip decoupling
Substrate
isolation
combined with resistive supply path
No rules to reduce
susceptibility
Work done at Eseo France
(Ali ALAELDINE)
Frequency
65
April 15
Golden Rules for Low susceptibility
Rule 2: Isolate Noisy blocks
Bulk isolation
Why ?
• To reduce the propagation of
switching noise inside the chip
• To reduce the disturbance of
sensitive blocks by noisy blocks
(auto-susceptibility)
How ?
• by separate voltage supply
• by substrate isolation
• by increasing separation between
sensitive blocks
• By reducing crosstalk and
parasitic coupling at package level
Noisy blocks
Standard
cells
Analog
Separate supply
66
April 15
Far from
noisy blocks
Golden Rules for Low susceptibility
Rule 2: Isolate Noisy blocks
separate
supply
substrate
isolation
increasing
separation
between sensitive
blocks
Barić , FER Zagreb
EMC Compo 2011
67
April 15
Golden Rules for Low susceptibility
Rule 3: Improve noise immunity of IOs
• Add Schmitt trigger on digital input buffer
• Use differential structures for analog and digital IO to reject common mode
noise
2 dB
Schmitt trigger
68
April 15
Design guidelines for EMC of IC
Case study – Starcore floorplan improvement

The Starcore is 16-bit micro-controller used in automotive industry:
•
16 bit MPU with 16 MHz external quartz, on-chip PLL providing internal 133 MHz
operating clock
•
128 Kb RAM, 3 general purpose ports (A, B, C, 8 bits), 4 analog inputs 12 bits,
CAN interface
SIGNAL
Description
VDD
Positive supply
VSS
Logic Ground
VDD_OSC
Oscillator supply
VSS_OSC
Oscillator ground
PA[0..7]
Data port A (programmable drive)
PB[0..7]
Data port B (programmable drive)
PC[0..7]
Data port C (programmable drive) external 66MHz data/address
CAN Tx
CAN interface (high power, 1MHz)
CAN Rx
CAN interface (high power, 1MHz)
XTL_1, XTL_2
Quartz oscillator 16MHz
CAPA
PLL external capacitance
RESET
Reset microcontroller
69
April 15
Design guidelines for EMC of IC
Case study – Starcore floorplan improvement

Several tests were conducted by the customer and a huge list of problems appeared.
Now that you learnt some rules about low emission floor-planning, you are probably
able to understand the origin of the listed problems. In this case study, you act as an
EMC engineer which is called urgently to improve the floor-planning of the chip
(without changing the chip layout which would cost too much), in order to save the
contract.

Warning:
•
Reliability problems (over current) on pin
•
23 Ground bounce: voltage drop around 500mV (spec: 50mV)
•
VDD bounce: voltage drop around 700mV (spec 50mV)
•
ADC measured resolution: 6 bits (required 10 bits)
•
CAN bus erratic problems
•
Oscillator PLL sometimes do not lock
70
Design guidelines for EMC of IC
SIGNAL
Description
Emission Susceptibility
Case
study – Starcore
floorplan
improvement
Remark
Assign to
A l’opposé, 1 seule
 The first action is to identify which block is a noisy block, which part is a sensitive part.
VDD
Positive supply
+
paire, sur les
diagonales
VSS
Logic Ground
+
Réassigner broches
VDD_OSC
Oscillator supply
+
+
Osc près Bloc Osc.
VSS_OSC
Oscillator ground
+
+
à éloigner du CAN
Data port A (programmable
PA[0..7]
drive)
Data port B (programmable
PB[0..7]
drive)
Data port C (programmable
Mettre une paire
PC[0..7]
drive) external 66MHz
Vdd/Vss à proximité
Paire alim dédiée
VddA/VssA,
+++
resolution)
repositionner près du
CAN interface (high power,
CAN Tx
1MHz)
CAN interface (high power,
CAN Rx
1MHz)
71
XTL_1, XTL_2 Quartz oscillator 16MHz
Design guidelines for EMC of IC
Case study – Starcore floorplan improvement

Then you can try to assign the various I/os to specific pins.
