PPTX Slides

Report
Dr A Sahu
Dept of Computer Science &
Engineering
IIT Guwahati
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Programmable Interface device (Introduction)
Requirement for programmable interface device
Simple example configurable device
Programmable Interface device 8155
– Block diagram
– Address diagram
– Interfacing LED using 8155
• 8155 Timer
– Modes of timer
– Square wave generation using 8155 interfaced timer
• Next class (8055 Handshake & Interrupt mode)
• Designed to perform various I/O functions
• Device can be setup to perform specific
functions
– By writing instruction to a internal register
• Can be changed during execution of the
program
• Devices are flexible, versatile & economical
• Functions are determined by software
instructions
• Can be viewed as multiple I/O device
• Perform many functions
– Time delay, counting, interrupts
• Consists of many devices on a chip,
interconnect through a common Bus
• Software programmable approach of I/O
reduce design time
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I/P & O/P Regs: A group of latches to hold data
Tri-State Buffer
Capability of Bidirectional data flow
Handshake & Interrupt signal
Control Logic
Chip Select Logic
Interrupt control logic
• Configurable Device Example
• Latch Direction
A
B
Direction
Chip
Select
7A
D7
A7
A6
A5
A4
A3
A2
A1
Control
Reg
D1
D0
7B
0A
0B
DIR
G:
Enable
A0
• Program
MVI
OUT
MVI
OUT
A,01 H ; Set Do=1, D1-D7==0
FFH
;Write in control register
A,BYTE1
;Load data bye
FEH
; Send Data out
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2kbits static RAM 256x8
2 programmable 8 bit I/O ports
1 programmable 6 bit I/O port
1 programmable 14 bit binary counter/timer
Internal address latch to Demux AD0-AD7,
using ALE line
Reset in
RD
WR
CE
IO/M
AD0-AD7
Port
A
PA0-PA7
RAM
Port
B
PB0-PB7
ALE
Port
C
8155
Timer
CLK
PC0-PC5
Timer
MSB LSB
Timer
Out
CEb
CWR
A2
A1
A0
Port (ALE
high,
AD0=A0)
0
0
0
Command
/Status
Register
0
0
1
PA
0
1
0
PB
0
1
1
PC
1
0
0
Timer LSB
1
0
1
Timer MSB
AD0-AD7
Latch
ALE
A2
D7-D0
Port
A
A0-A7
A1
A0
0
1
3 to 8 2
3
Decoder 4
5
PA0-PA7
Port
B
PB0-PB7
Port
C
PC0-PC5
Timer
MSB LSB
Clock for timer
Timer
Out
5V
A15
A14
A13
A12
A11
A2
A1
A0
3 to 8 04
Decoder
Reset in
RD
WR
CE
IO/M
Con
trol
20H
CWR
IO/
M
Latch
A0-A7
Port
A
RAM
AD0-AD7
21H
ALE
D7-D0
A
2
A
1
A
0
22H
3 to 8
Decoder
Port
B
PA0-PA7
PB0-PB7
23H
Port
C
CS
PC0-PC5
Timer
MSB
LSB
Clock for timer
24H
25H
Timer
Out
Reset in
RD
WR
CE
IO/M
Con
trol
20H
IO/M
Latch
A0-A7
Port
A
RAM
AD0-AD7
21H
ALE
A2
8155
CWR
D7-D0
A1
3 to 8
Decoder
22H
PA0-PA7
Port
B
PB0-PB7
Port
C
PC0-PC5
23H
A0
Timer
MSB LSB
Clock for timer
24H
25H
Timer
Out
D7
D6
Timer Command
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D5
D4
IEB
IEA
D3
D2
PC
D1
D0
PB
PA
D0, D1: mode for PA and PB, 0=IN, 1=OUT
D2, D3: mode for PC
D4, D5: interrupt EN for PA and PB, 0=disable 1=enable
D6, D7: Timer command:
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–
–
–
00: No effect
01: Stop if running else no effect
10: Stop after terminal count (TC) if running, else no effect
11: Start if not running, reload at TC if running.
• Port C bits
(D2, D3)
ALT D3 D2
PC5
PC4
PC3
PC2
PC1
PC0
1
0
0
IN
IN
IN
IN
IN
IN
2
0
1
OUT
OUT
OUT
OUT
OUT
OUT
3
1
0
OUT
OUT
OUT
STBA
BFA
INTRA
4
1
1
STBB
BFB
INTRB
STBA
BFA
INTRA
5V
A15
A14
A13
A12
A11
AD7
to
AD0
A2
A1
A0
3 to 8 04
Decoder
8155
IO/Mb
ALE
RDb
WRb
RESET OUT
IO/Mb
ALE
RDb
WRb
RESET OUT
PA7
PA6
PA5
PA4
7 Seg
LED
Driver
PA3
PA2
PA1
PA0
7 Seg
LED
Driver
PB7
PB6
PB5
PB4
7 Seg
LED
Driver
PB3
PB2
PB1
PB0
7 Seg
LED
Driver
• Port Address
– Control Register=20H, Port A= 21H, Port B= 22H
• Control word:
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
1
1
Port B
Output
Port A
Output
Timer
Not
Applicable
Use for
Port C
• Program
–
–
–
–
–
–
MVI
OUT
MVI
OUT
MVI
OUT
A,03
20H
A, BYTE1
21H
A, BYTE2
22H
; initialize Port A &B for O/P
; Display BYTE1 at port A
; Display BYTE2 at port B
• R S Gaonkar, “Microprocessor
Architecture”, Chapter 14

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