Comprehensive Metrics Driven Methodology to Measure and

Report
A Comprehensive Metrics
Driven Methodology to
Measure and Improve
Soft-IP Quality
Anuj Kumar - Atrenta
Andy Wu - TSMC
This presentation may contain forward-looking statements regarding product development. Information or statements contained in this presentation are for informational
purposes only and do not represent a commitment, promise, or legal obligation of any kind by Atrenta Inc. or its affiliates.
DAC 2014 - IP Track Submission
Background and Motivation
Standardize IP Handoff & Acceptance Quality Checks
 To define a comprehensive set of quality checks to assess the implementation
readiness for soft IPs to enable a smooth IP handoff / acceptance flow.
 These quality checks are derived from Atrenta’s Reference GuideWare 2.0 Methodology
for IP and SoC RTL Signoff and later renamed as “TSMC Soft IP Quality Golden Rules”
 TSMC Soft IP Quality Checks should be equally applicable for different types of Soft IP
e.g. internal, legacy, or 3rd party RTL IPs / Blocks
Enable Easy Adoption of the Flow to Benefit a Wide Variety of IP-SoC Ecosystem
Partners
 The IP Qualification flow should be easy to setup
 Get to the meaningful (high coverage low noise) results with self guided and systematic
approach
Provide Portable, Easy to Read / Correlate, and Quality Metrics Objective-based
Handoff / Acceptance Reports
Flow Should be Scalable and Easy to Integrate in Existing Design Flow
Environments
DAC 2014 - IP Track Submission
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Overview of TSMC 9000 Soft IP Qualification Program
TSMC
Online
IP Ecosystem
Partners
IP supplier 1
Atrenta
DashBoard
End Customers
IP1
Chip project 1
IP 2
IP supplier 2
TSMC IP
Kit
IP supplier 3
IP 3
Chip project 2
TSMC IP
Kit
Chip project 3
Handoff
…
IP supplier n
DAC 2014 - IP Track Submission
IP n
Atrenta
DataSheet
Inspection /
Acceptance
…
Chip project n
3
TSMC
IP IP
Handoff
KitKit
TSMC
Handoff
IP
TSMC IP Handoff Kit
Doc, training, scripts
Physical
Constr
Power
DFT
Lint
CDC
GuideWare goals
IP reports
waivers
UPF/CPF
FSDB,…
SDC
SGDC
RTL
IP Design Intent
….
Quickstart Training Scripts,
Guide
module setup
Atrenta
DataSheet
Atrenta
DashBoard
Deliverables
SpyGlass Clean
IP
DAC 2014 - IP Track Submission
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TSMC IP Handoff Kit – Inputs / Outputs
TSMC IP Handoff Kit
Project file
TSMC IP Handoff
Methodology
Tech Libs
(.lib)
Std. Design
Constraints
Simulation Inputs
(SDC, VCD/FSDB,
UPF/CPF)
SGDC file
SpyGlass
Waiver file
Other setup
files
RTL
(.v/.sv/.vhd)
IP Handoff Deliverables
RTL+TechLibs
Design Analysis/Quality Metrics Reports
RTL
Tech Libs
CDC
Fault Covg
Power
DataSheet
DashBoard
moresimple
count
Sign_off
SpyGlass Setup Files
SpyGlass
Project File
(.prj)
Waivers
(.swl)
SGDC
SDC
UPF/CPF
VCD/FSDB/SAIF
SDC
Coverage
DAC 2014 - IP Track Submission
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Key Soft IP-Kit Quality Checks
 Best practices lint checks
 IP readiness for simulation & synthesis analysis
 Identification of deadcode, x-assignment, unreachable states
 Multi mode/corner/design scenarios RTL Power Estimation
 Power Intent(UPF/CPF) verification
 Fault/Test Coverage Analysis (Stuck@ & Transition)
IP
TSMC IP Kit
SG-Lint
SG-AdvanceLint
SG-Power
SG-PowerVerify
 Clock/Reset Propagation (Glitch, convergence) Analysis
SG-DFT
 Asynchronous Clock Domain Crossing Path Verification
SG-Clocks
 Timing constraints(SDC) checks for completeness & consistency
 Verification of Timing Exceptions(FP,MCP)
 Area, timing(negative slack paths) & congestion analysis
SG-Constraints
SG-Txv
SG-Physical
SpyGlass Clean
IP
DAC 2014 - IP Track Submission
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TSMC IP Kit Execution Flow
Design Read
>% aipk_read -top foo –srcfile foo.f –libfile lib.f –sdcfile foo.sdc
-activity_file foo.vcd
Design Setup Checks
>% aipk_read –top foo
Basic Design Checks
>% aipk_run –top foo –goals basic_check
Advanced Design Checks
>% aipk_run –top foo –goals adv_check
IP Packaging
 Auto-generation of SpyGlass setup files
(.prj, .sgdc, .swl, .dat ,etc.)
 Generation of Design Read DashBoard report
 Ensures that RTL is read in successfully
 Identifies unconstrained clock/resets in the
design
 Ensures that design setup is complete &
correct
 Runs basic IP handoff checks (Lint, CDCStructural, DFT, SDC, Power)
 Generates quality report for basic design
checks/goals
 Runs advanced IP handoff checks (CDC
functional, Lint functional & physical)
 Generates overall quality report combining
results for basic & advanced checks
 Packages an IP with design intent, setup &
analysis reports
>% aipk_pack –top foo –save_all
DAC 2014 - IP Track Submission
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Soft IP Quality Metrics DashBoard Report
DAC 2014 - IP Track Submission
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IP Specification/Datasheet Report
TSMC IP Kit generates the SpyGlass DataSheet report capturing key design
specifications and profile statistics, once all goals run are finished
Design
Read
DAC 2014 - IP Track Submission
Design
Setup
Check
Design
Analysis
IP
Packaging
9
Sample Results from TSMC IP Kit Analysis
IPStats
Test
Power
% ports constrained
% registers constrained
No. of unverified FP
No. of unverified MCP
Internal (mW)
Leakage (uW)
Switching (mW)
21885
8817
462 130
22
98
8668514 2154640 46637 36
212
88
639021 227585 8907 22027 40626 99
57000
23000 2537 275
757
100
95000
39000 9000 4279 1387 100
110000
47000 4806 2552 3802
99
2201603 489245 94023 12
47
98
907303 210201 59125 121
65
99
70439
20125 4546 1300 523 99.7
SDC
Test
Coverage(transition@)
Test Coverage(stuck@)
Synchronized CDCs
Unsynchronized CDCs
Flop Count
Instance Count
Gate Count
Core-1
Vendor A
Vendor B
Vendor C -IP1
Vendor C-IP2
Vendor C-IP3
Vendor D-IP1
Vendor D-IP2
Vendor E-IP1
…
CDC
94.3
85.3
92.3
98.7
91.2
94.1
91.8
91
94.9
98
65
81
98
89
99
99
100
100
100
100
100
100
99
100
100
100
100
0
0
0
2
0
0
0
0
0
0
0
0
0
0
0
2
0
8
4
65
23
11
40
12
118
117
9.46
72.9
350
2880
13.9
21.7
24.2
1870
8140
64.2
2.3
79
15
4.9
65
12
115
20
0.95
30+ Soft IPs qualified from 20 different IP vendors enrolled in
the TSMC Soft IP 9000 Program so far….
DAC 2014 - IP Track Submission
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TSMC IP Kit – A Typical User Adoption Flow
IP1
IP1
Legacy
IP
STANDARDIZED IP INSPECTION
IP1
IP1
Legacy
IP blocks
IP1
IP1
New
RTL blocks
IP1
IP1
3rd party IP
IP Suppliers
TSMC IP
Kit
IP1
IP1 RTL
New
IP1
IP1
3rd party IP
blocks
Atrenta DataSheet
Atrenta DashBoard
+
IP design intent
HIGH QUALITY IP
BLK 1
BLK 2
SoC Integrators
BLK3
SMOOTH SoC INTEGRATION
DAC 2014 - IP Track Submission
BLK n
SoC
MINIMIZE ITERATIONS
11
TSMC IP Kit – User Benefits
Standardized inspection flow for all
IPs including ones from internal
sources (new, legacy, older designs)
Propagate IP design intent –
SDC/SGDC, waivers, *PF, … for
chip integration
Beyond functional verification…
 Maximize internal IP re-use
 IP integrates efficiently
 Fully verified IP
Automated regression flow runs
the IP kit nightly and generates
DataSheet & DashBoard reports
 Automatically track IP
updates/ bug fixes
DAC 2014 - IP Track Submission
Verify IP for CDC, SDC, DFT,
*PF, …
Review DataSheet and DashBoard to
select the correct IP
Create an IP repository with
published reports
 IP selection based on
objective quality & spec metrics
 Streamline IP delivery
and track usage
12
Summary / Conclusion
SpyGlass, TSMC Soft IP Quality Golden/GuideWare Rules and Atrenta
Design analysis reports(DashBoard/DataSheet) together provide
a comprehensive, detailed and design objective based Soft-IP quality
assessment report.
TSMC and Atrenta have partnered to adapt these tools for TSMC’s soft IP
9000 Qualification Program.
A comprehensive set of quality checks, as included in TSMC IP Kit, has
been defined and documented in Design Metric Reports.
TSMC IP Kit Flow successfully adopted by 20+ IP ecosystem partners,
which was quite helpful in improving the implementation readiness for
their various Soft-IPs.
Summary results of IPs for IP ecosystem partners are posted on TSMC
Online
DAC 2014 - IP Track Submission
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