ppt - Embedded Systems and Codesign Laboratory

Report
Virtual Prototyping with Carbon Design
Tools
Aalap Tripathy, Rabi Mahapatra
Embedded Systems Codesign Lab
http://codesign.cse.tamu.edu
Overview
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SoC’s today
SoC design paradigm
SoC design issues
Virtual prototyping benefit
Virtual Prototyping options
What is a “Carbon model”?
Tools used & their interplay
Assignments Flow
Resources
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Overview
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SoC’s today
SoC design paradigm
SoC design issues
Virtual prototyping benefit
Virtual Prototyping options
What is a “Carbon model”?
Tools used & their interplay
Assignments Flow
Resources
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SoC’s today
Single chip DVR- 4 channel MPEG 4 DVR SoC
SoC’s today
802.11b radio, MAC, baseband processor, pn-chip flash, ARM Applications Processor
SoC’s today
Tablet/Smart TV/Thin Client SoC – ARM Applications Processor, Video Interface, CMOS Sensor Input, USB,
Audio Interface (I2S, S/PDIF), SPI, I2C, UART, GPIOs
SoC’s today
Smartphone/Tablet SoC – ARM Mali 400 (single core) graphics card, Video Processing Unit, Audio Interface,
Webcam Interface, Video Interface etc.
SoC’s today
Server SoC – ARM Quad Core
Overview
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SoC’s today
SoC design paradigm
SoC design issues
Virtual prototyping benefit
Virtual Prototyping options
What is a “Carbon model”?
Tools used & their interplay
Assignments Flow
Resources
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SoC design paradigm
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System Realization
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SoC Realization
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Concerns for SoC Architect
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How to validate SoC design?
How to reduce risk? – Reuse IP
How to convey design intent to software development team? – Design is still in flux.
How to convey design impact to end-customer? – Black-box parts of design
How to quickly detect system corner cases?
Architecture for
semiconductor
defined
IP blocks chosen
Design matured
Silicon Realization
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System
requirements
defined in h/w and
s/w
Design
implemented in
Silicon
SoC design paradigm
Overview
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SoC’s today
SoC design paradigm
SoC design issues
Virtual prototyping benefit
Virtual Prototyping options
What is a “Carbon model”?
Tools used & their interplay
Assignments Flow
Resources
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SoC design issues
MIPI
CPU(s)
GPU
USB3
Ethernet
HDMI
WLAN
GPIO
PCIe
IP Selection
• Which vendor?
• Which IP?
• Will they all play together?
UART
Without Cycle Accurate Modeling
• Forced to believe IP marketing
• SoC may not meet spec
• Can’t benchmark till purchase
CPU(s)
GPU
CCI/NoC
USB3
Ethernet
NoC/Fabric
PCIe
Interconnect Architecture
• CCI vs. NOC vs. Fabric?
• Make or buy?
• How many?
• What configuration(s)?
Periph Fabric/NoC
SoC design issues
MIPI
HDMI
WLAN
GPIO
UART
Without Cycle Accurate Modeling
• No validation between layout and
performance
• Inefficient power consumption
• Missed performance spec
• Waste power with overdesign
CPU(s)
GPU
USB3
Ethernet
L2 Cache
CCI/NoC
NoC/Fabric
DDRx
PCIe
Memory subsystem
• Cache sizing
• How big?
• Which memory technology?
• System performance impact?
Periph Fabric/NoC
SoC design issues
MIPI
HDMI
WLAN
GPIO
UART
Without Cycle Accurate Modeling
• Wasted die space on
overdesigned cache
• Poor cache performance
• Overspend on IP
• Wasted power
SoC design issues
GPU
USB3
Ethernet
L2 Cache
CCI/NoC
NoC/Fabric
DDRx
PCIe
Firmware Development
• Pre-silicon firmware
development
• Software performance analysis
• System integration issues
Periph
Fabric/NoC
MIPI
CPU(s)
HDMI
WLAN
GPIO
UART
Without Cycle Accurate Modeling
• No guarantee of software
running on first day silicon
• Inability to tune hardware/
software performance
• Chip re-spin – huge cost
SoC design issues
Internal Users
External Users
USB3
Ethernet
L2 Cache
CCI/NoC
NoC/Fabric
DDRx
PCIe
MIPI
HDMI
CPU(s)
WLAN
L2 Cache
GPU
USB3
Ethernet
GPIO
CCI/NoC
NoC/Fabric
UART
DDRx
PCIe
Deployment
• Secure platform for external
users
Periph
Fabric/NoC
GPU
Periph
Fabric/NoC
MIPI
CPU(s)
HDMI
WLAN
GPIO
UART
Without Cycle Accurate Modeling
• Can’t black-box feature sets.
• Can’t share with end customer
• IP exposure
• Design intent lost
Overview
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SoC’s today
SoC design paradigm
SoC design issues
Virtual prototyping benefit
Virtual Prototyping options
What is a “Carbon model”?
Tools used & their interplay
Assignments Flow
Resources
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Virtual Prototyping Benefit
Prototyping Options
Traditional
Virtual
Prototype
Early
Availability
Speed
Accuracy
HW Debug
SW Debug
Execution
Control
Extra Devel
Effort
Replication
Cost
RTL
Simulation
Emulation
FPGA
Based
Prototypin
g
Silicon
Carbon
SoC
Designer
Overview
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SoC’s today
SoC design paradigm
SoC design issues
Virtual prototyping benefit
Virtual Prototyping options
What is a “Carbon model”?
Tools used & their interplay
Assignments Flow
Resources
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What is a Carbon Model?
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What is a Carbon Model?
– A high performance linkable software
object
– Generated by proprietary compiler from
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synthesizable RTL design files
options & directives files
– Contains cycle-accurate & registeraccurate description of hardware
design
– Organized in the form of:
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Software Object file (libdesign.a on Linux or
libdesign.lib on Windows)
Header file (libdesign.h)
Binary database (libdesign.symtab.db) –
database with information about all internal
signals
Using a Carbon Model
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Linked with gcc (or Microsoft VC++)
Libcarbon5.so & carbon_capi.h are part of
installation on Linux
Simulator communicates with hardware
model through sockets using carbon_capi.h
Tools you will be using
http://www.carbondesignsystems.com/carbon-modelstudio/
http://www.carbondesignsystems.com/soc-designerplus/
Carbon Model Studio
Carbon SoC Designer
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Enables carbon model
creation from RTL
– Verilog/VHDL/Syste
mC
Virtual Prototyping Canvas
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Assemble system
Drive system
Debug
Analyze (profile)
Optimize
http://www.carbondesignsystems.com/performance-analysis-kits/
CPAK
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Carbon Performance Analysis
Kits
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Ready-to-use assembly of
processor models + IP
blocks + baremetal/OS +
benchmarking tools
Interplay between tools
State Machine design
Firmware
development/source
code
RTL
System Level
Model
μP
CA
Model
Model
LT
CA
LT
Model
Model
Model
Co-simulation
Other IP Models
What will tools enable?
Architectural Analysis
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Analyze memory subsystems
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Analyze system throughput & latency
Validate bus & pipeline performance
assumptions
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Software function profiling
Synchronization & timing
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Zero silicon design & validation
Validate HW/SW partitions
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Analyze cache statistics
Will arbitration logic work as expected?
Enables quick re-configurability & rerun of SoC design
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Feature change is easy
What will tools enable?
Firmware Validation &
Application software
development
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Begin firmware development even while
SoC is in “concept” stage.
Use the same platform as SoC
hardware & software designs mature
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Integrated debug tools for hardware &
software
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Maximize design reuse
Analyze impact of software on hardware
performance & vice versa
Have complete system visibility
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Set breakpoints in firmware debugger or in
hardware
Interrupt SoC operation at any point to examine
behavior
Overview
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SoC’s today
SoC design paradigm
SoC design issues
Virtual prototyping benefit
Virtual Prototyping options
What is a “Carbon model”?
Tools used & their interplay
Assignments Flow
Resources
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Assignments Flow
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Introduction to SoC Designer
– Construct & Debug an ARM Cortex A9 Bare-metal SoC
– Understand the role of IP blocks/components necessary to design a system
– Run an example sort application (insertion & bubble sort)
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Introduction to Model Studio
– Create a carbon model from RTL (Vectored Interrupt Controller)
– Write RTL for a APB compatible timer, create carbon model, integrate into ARM
Cortex A9 Baremetal SoC
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Introduction to Co-simulation
– Export Interrupt Controller signals into Modelsim simulation kernel from SoC
Designer.
– Use Interrupt Controller RTL & Top level test-bench to drive SoC Designer
– Perform co-simulation for APB compatible timer
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• Compilation & Simulation of Applications
– How to create, compile, run and characterize an application on SoC Designer
– “Hello World” & Vector multiplication – How to create an ARM Executable file
(axf)
– Profile software code, observe bus level transactions & correlate to source
code
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Interplay between tools
State Machine design
Firmware
development/source
code
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RTL
System Level
Model
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μP
CA
Model
Model
LT
LT
LT
Model
Model
Model
Co-simulation
Other IP Models
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Example
ARM Cortex A9 Demo SoC
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ARM application processor connected via an AXIv2 bus to program & data memory. Memory
mapped IO
Bridge to APB bus  connects to timer, Bridge to AHB bus  connects to interrupt controller
Core for processor compiled from ARM RTL, supports 32 kb Instruction Cache, 32kb Data
cache, 128 KB TLB, no Floating Point Unit, does not contain Neon Media Processing Engine
AMBA – de-facto standard for on-chip communication, open standard – Learn more.
Who else is using these tools?
Resources
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ARM InfoCenter - http://infocenter.arm.com/
Carbon Tutorials - /opt/carbon_tutorials
Component User Guides - /opt/documents
ARM Specs - /opt/documents/arm_specs/
Carbon Tool User Guides - /opt/SoCDesigner/doc/
ModelSim User Guide - /opt/ModelSim-SE10.d/modeltech/docs/pdfdocs/modelsim_se_tut.pdf
• Please DO NOT register on Carbon Design Systems website.
The models you may need for projects will be provided to you
• Contact for tool-related issues:
– Prof. Rabi Mahapatra ([email protected])
– Deam Ieong ([email protected])
Conclusion
• Virtual prototyping tools can help accelerate
– Architectural exploration
– Firmware development
– System integration & customer integration
• Familiarity & expertise with these tools will help
– Job-relevant skills
– Gain experience with ARM-based SoC, AXI
– Experience switched fabrics and network topology
Acknowledgement

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