Report

Ch 6. Combinational Logic Design Practices 6.1 Documentation standards The type of documentation depends on system complexity and the engineering and manufacturing environments, a documentation package should generally contain at least the following six item: 1. 2. 3. 4. 5. 6. Specification ( I/O, function ) Block diagram ( pictorial description ) Schematic diagram (electrical components, interconnection IC type) Timing diagram (logic signals as a function) Structured logic device description ( logic equations, state tables/diagram) Circuit description ( narrative text document) 6.1.1 Block Diagrams Control Signal 6.1.2 Gate Symbols A B F F = (A’ * B’)’ = A’’ + B’’ = A + B 6.1.3 Signal Names and Active Levels 6.1.4 Active Levels for Pins 6.1.4 Active Levels for Pins 6.1.5 Bubble-to-Bubble Logic Design 6.1.5 Bubble-to-Bubble Logic Design (A * SEL)’ (B * SEL’)’ = ((A*SEL)’ * (B * SEL’)’)’ = A*SEL + B*SEL’ (Hard to read) (Easy to read) 6.1.5 Bubble-to-Bubble Logic Design 6.1.7 Drawing Layout 6.1.8 Buses 6.1.8 Buses 6.1.8 Buses / 16 /8 /8 6.1.9 Additional Schematic Information 6.2 Circuit Timing Most digital systems are sequential circuits that operate step-by-step under the control of a periodic clock signal, and the speed of the clock is limited by the worst-case time that it takes for the operations in on step to complete. Thus digital designers need to be keenly aware of timing behavior in order to build fast circuits that operate correctly under all conditions 1. 2. 3. 4. 5. Timing Diagrams Propagation Delay Timing Specifications Timing Analysis Timing Analysis Tools 6.2.1 Timing Diagrams Causality 6.2.1 Timing Diagrams Uncertain transition 6.2.2 Propagation Delay Vin Vout - maximum/minimum delay - typical : average - worst-case delay tpHL tpLH ex) 99% good IC, CKT with 100 IC 100 (1 - 0.99 ) x 100 = 63% ( would not work) = sum of worst case delay through individual component = max. delay 6.2.3 Timing Specifications The timing specification for a device may give minimum, typical, and maximum values for each propagation-delay path and transition direction 6.3 Combinational PLDs 6.3.1 Programmable Logic Arrays : PLA # of inputs (n) # of outputs (m) # of product term (P) ‘ n X m PLA with P product term ‘ Contains p AND gates(2n-input) and m OR gates(p inputs) - 2n-input AND gate -> p P-input OR gate -> m - → PLA fuses are ‘x’ in the figure and nonvolatile memory cells. → They are programmed. 2n = true or complement of input 6.3.1 Programmable Logic Arrays 6.3.1 Programmable Logic Arrays O1 = I1·I2 + I1´·I2´·I3´·I4´ O2 = I1·I3´ + I1´·I3·I4 + I2 O3 = I1·I2 + I1·I3´ + I1´·I2´·I4´ P1 P2 = I1*I2 + I1’*I2’*I3’*I4’ 6.3.1 Programmable Logic Arrays 6.3.2 Programmable Array Logic Devices 6.3.3 Generic Array Logic Devices [Ex-2] GAL16L8 : Fig 27 input output • XOR gate between OR and inverter output polarity = if fuse -> intact, XOR = AB+AB (B =0) = A (PASS) -> blown , XOR = AB+AB (B=1) = A ( inverting) 6.3.4 Complex Programmable Logic Devices(CPLDs) Chapter 9 6.3.5 CMOS PLD Circuits i) AND-OR diode logic 5V A A X = A·B B B • fusible link, high voltage ( 10~30V ) -> OFF • masked programmed PLD -> ROM X = A+B 6.3.5 CMOS PLD Circuits ii) CMOS PLD CKTs < AND plane > < OR plane > 6.3.5 CMOS PLD Circuits iii) erasable PLD accumulated charge at high volt(25V) ultra-violet light -> erase floating gate ( change storage device) 10 years -> 70% decay Ex) PLD writer : PLD programmer and testing (test vector generation) 6.4 Decoder A decoder is a multiple-input, multiple-out logic circuit that converts coded inputs into coded outputs, where the input and output codes are different 1. 2. 3. 4. Binary Decoders Logic Symbols for Larger-Scale Elements The 74x138 3-to-8 Decoder Decoders in VHDL 6.4.1 Binary Decoder n - 2 decoder n bit binary input code n 1 out of 2 output code 6.4.1 Binary Decoder P.52 [Fig6] Gary code 6.4.3 The 74x138 3-to-8 Decoder Y5 = G1*G2A*G2B*CB’A Enable Select 6.4.3 The 74x138 3-to-8 Decoder G2A = G2A_L’, G2B = G2B_L’, Y5 = Y5_L’ Y5 = G1 * G2A * G2B * CB’A Y5_L = G1’ + G2A_L + G2B_L +C’ + B + A’ 6.4.3 The 74x138 3-to-8 Decoder • 3 enable inputs : G1, G2A , G2B • ex) Y5 = G1· G2A · G2B·A·B·C because of inversion bubble on Y5 Y5´ = (G1· G2A · G2B·A·B·C)´ = G1´+ G2A + G2B+A+B+C 6.4.4 Cascading Binary Decoders higher order decoder : tree decoding • 4 select inputs : N0 N1 N2 N3 + 1 enable EN • SN74154 ( 1 out of 16 decoder ) 6.4.4 Cascading Binary Decoders 3LSBs 2MSBs N4*N3 = 00,Y0’ = L N4*N3 = 01,Y1’ = L N4*N3 = 10,Y2’ = L N4*N3 = 11,Y3’ = L 6.4.6 Decoder in VHDL Entity : Simply a declaration of a module’s inputs and outputs Architecture : a detailed description of the module’s internal behavior or structure 6.4.6 Decoder in VHDL When A = 010, then Y_L_i = 11011111 When G1*G2A’’*G2B’’ = G1*G2A_L’*G2B_L’ 6.4.6 Decoder in VHDL Active-level handling 6.4.6 Decoder in VHDL 6.4.6 Decoder in VHDL 6.4.6 Decoder in VHDL Instead of Table 6-17 Dataflow definition, Behavior Model uses a process and sequential statements 6.4.6 Decoder in VHDL Page268 Table5-25 Convert std_logic_vector to integer 6.4.6 Decoder in VHDL 6.4.6 Decoder in VHDL 6.5 Encoder A decoder’s output code normally has more bits than its input code. If the device’s output code has fewer bits than the input code, the device is usually called an encoder 1. 2. 3. Priority Encoders The 74x148 Priority Encoder Encoders in VHDL 6.5.1 Priority Encoders = I1 + I3 + I5 + I7 = I2 + I3 + I6 + I7 = I4 + I5 + I6 + I7 6.5.1 Priority Encoders - 2n inputs each indicates a ‘request’ for service (=interrupt request) - priority encoder each request has a priority -ex) 8-to-3 encoder : 74x148 (I7 = highest priority) idle : if no input 6.5.2 The 74x148 Priority Encoder -logic symbol : · EI : enable input · Gs : assert if Enable and more than 1 input assert (group select) · E0 : enable output : connect to EI input of another 148 6.5.2 The 74x148 Priority Encoder Ex) 15 input priority encoder · 215 possible input combinations 6.5.2 The 74x148 Priority Encoder If REQ30_L = 0, otehrs = 1 Then G3A2_L * G3A1_L * G3A0_L = 001 G3GS_L = 0, G3E0_L = 1 6.5.4 Encoder in VHDL Initialization When GS asserted, E0 deasserted 6.6 Three-State Devices In Section 3.7.3 we described the electrical design of CMOS devices whose outputs may be in one of three states 0,1,Hi-z. In this section we’ll show how to use them 1. 2. 3. Three-State Buffer Standard MSI Three-State Buffer Three-State Outputs in VHDL 6.6.1 Three-State Buffers = If SELP_L = 0, SDATA = P when ABC = ‘000’ 6.6.1 Three-State Buffers Turn-ON time · tpLZ or tpHZ < tpZL or tpZH : to avoid fighting (= drive by two device) Turn-OFF time · dead time safe way to use 3-state devices to guarantee during the dead time, no one IO driving 6.6.2 Standard MSI Three-State Buffers 6.6.2 Standard MSI Three-State Buffers When RD_L = 0, SEL1_L = 0, SEL2_L = 1, PORT1 UP When RD_L = 0, SEL1_L = 1, SEL2_L = 0, PORT2 UP 6.6.2 Standard MSI Three-State Buffers 6.6.2 Standard MSI Three-State Buffers When ENTFR_L = G’ = L & ATOB = DIR = 1 Bus A -> Bus B When ENTFR_L = G’ = L & ATOB = DIR = 0 Bus B -> Bus A 6.6.4 Three-State Outputs in VHDL Unresolved type 6.6.4 Three-State Outputs in VHDL 6.6.4 Three-State Outputs in VHDL 6.7 Multiplexers A multiplexer is a digital switch it connects data from one of n sources to its output. Figure 6-57(a) shows the inputs and outputs of an n-input, b-bit multiplexer. 1. Standard MSI Multiplexers 2. Expanding Multiplexers 3. Multiplexers, Demultiplexers, and Buses 4. Multiplexers in VHDL 6.7.1 Standard MSI Multiplexers EN Selcet(A,B,C) Data(D0~D7) Y 3 8 8x1 MUX output Y 6.7.1 Standard MSI Multiplexers 6.7.2 Expanding Multiplexers 6.7.3 Multiplexers, Demultiplexers, and Buses 6.7.3 Multiplexers, Demultiplexers, and Buses 6.7.5 Multiplexers in VHDL A B 8 Y C D 8 EN Sel(S1S0) output enable 6.7.5 Multiplexers in VHDL - use case statement A B 8 Y C D 8 EN Sel(S1S0) output enable 6.7.5 Multiplexers in VHDL 6.8 Exclusive-Or Gates and Parity Circuits 1. 2. 3. 4. Exclusive-OR and Exclusive-NOR Gates Parity Circuits Parity-Checking Applications Exclusive-OR Gates and Parity Circuits in VHDL f = XY + XY = XY + XY = XY· XY = (X + Y)(X + Y) = XY + XY = XY·XY = (X+Y)(XY) = (X + Y)(X + Y) X X Y f Y f X Y f=X+Y 6.8.1 Exclusive-OR and Exclusive-NOR Gates 6.8.2 Parity Circuits -odd parity and even parity ex) odd parity circuits ex) Even parity circuits output inverted 6.8.4 Parity-Checking Applications 74x280 9 bit parity generator : even and odd parity check 6.8.4 Parity-Checking Applications • error detecting code between memory and micro processor ex) parity generation and checking for an 8-bit-wide memory system When read, parity checking When write, parity generation 6.8.4 Parity-Checking Applications Ex) error correcting code for Hamming code Hamming Code : 1 2 3 4 5 6 7 8 10 … P P D P D D D P D … Check : C0 = 1, 3, 5, 7, 9, … C1 = 2, 3, 6, 7, 10, 11, … C2 = 4, 5, 6, 7, 12, 13, … 6.8.6 Exclusive-OR Gates and Parity Circuits in VHDL 6.8.6 Exclusive-OR Gates and Parity Circuits in VHDL First bit XOR P=1, if ODD 6.8.6 Exclusive-OR Gates and Parity Circuits in VHDL Table 6-41 Y = A + B + C 6.8.6 Exclusive-OR Gates and Parity Circuits in VHDL 6.9 Comparators Comparing two binary words for equality is a commonly used operation in computer systems and device interfaces 1. 2. 3. 4. 5. Comparator Structure Iterative Circuits An Iterative Comparator Circuit Standard MSI Magnitude Comparators Comparators in HDLs 6.9.1 Comparator Structure - 74x86 4bit comparator ex) magnitude comparator : SN74LS85 G = “A > B” E = “A = B” L = “A < B” A = A3 A2 A1 A0 B = B3 B2 B1 B0 6.9.2 Iterative Circuits primary input and output upper inputs and lower output cascading input and output between stage boundary input and output left and right most 6.9.3 An Iterative Comparator Circuits 6.9.4 Standard MSI Magnitude Comparators 74LS85 : 4 bit magnitude comparator Xi = Ai Bi + Ai Bi E = X3 X2 X1 X0 (i = 0, 1, …) ; equivalence G = A3 B3 + X3 A2 B2 + X3 X2 A1 B1 + X3 X2 X1 A0 B0 L = A3 B3 + X3 A2 B2 + X3 X2 A1 B1 + X3 X2 X1 A0 B0 GT = (A>B) + (A=B)·AGTBin EQ = (A=B)·AEQBin LT = (A<B) + (A=B)·ALTBin 6.9.4 Standard MSI Magnitude Comparators 12 bit comparator using 74 x 85 6.9.4 Standard MSI Magnitude Comparators PEQQ = 0 if all 8 bit pairs equal PGTQ = 0 if p[7 ~ 0] > Q[7 ~ 0] 6.9.4 Standard MSI Magnitude Comparators 8 bit MSI comparator 6.9.7 Comparators in VHDL Initialize 6.9.7 Comparators in VHDL 6.10 Adders, Subtractors, and ALUs Addition is the most commonly performed arithmetic operation in digital systems. An adder combines two arithmetic operands using the addition rules described in Chapter 2. 1. 2. 3. 4. 5. 6. 7. 8. Half Adders and Full Adders Ripple Adders Subtractors Carry-Lookahead Adders MSI Adders MSI Arithmetic and Logic Units Group-Carry Lookahead Adders in VHDL X X C C Y Y HA S S 6.10.1 Half Adders and Full Adders Sum = A(BC+BC) + A(BC + BC) = A(B + C) + A(B + C) =A+B+C Carry = ABC + ABC + ABC + ABC = C(AB + AB) + AB = C(A + B) + AB = BC + AC + AB 6.10.2 Ripple Adders A = A3 A2 A1 A0 4 + B = B3 B2 B1 B0 4 C Cout 4 bit adder 4 Cin S3 S2 S1 S0 6.10.3 Subtractor full subtractors : x – y – Bin B & D X : minuend Y : Subtrahend D = XYBin + XYBin + XYBin + XYBin Bin : borrow in = X(Y + Bin) + X(Y + Bin) Bout : borrow out D : difference = X + Y + Bin B = XYBin + XYBin + XYBin + XYBin = X(Y + Bin) + YBin) = XY + XBin + YBin - 2’s Complement subtractor : X – Y = X + Y +1 6.10.3 Subtractor 6.10.4 Carry-Lookahead Adders one stage carry lookahead adder Si = Xi + Yi + Ci Ci+1 = XY + XCi + YCi = XY + (X + Y)Ci carry lookahead factor · carry generator : if Xi = Yi = 1, Ci+1 = 1 Gi = Xi ·Yi independent of the input · carry propagate signal Pi = Xi + Yi · Ci+1 = gi + piCi two level AND-OR expression X0 ~ Xi-1 Y0 ~ Yi-1 6.10.5 MSI Adders 74x283 4-bit binary adder 6.10.5 MSI Adders 74x283 4-bit binary adder i) half sum equation : hsi Hsi = Xi + Yi = XiYi + XiYi = XiYi + XiXi + XiYi + YiYi + (Xi + Yi)(Xi + Yi) = (Xi + Yi)(XiYi) = pi qi ii) carry equation Ci+1 = pi ·qi + pi ·Ci = pi ·(qi + Ci) 6.10.6 MSI Arithmetic and Logic Unit 16 bit group ripple adder 4 bit carry lookahead adder + carry 6.10.6 MSI Arithmetic and Logic Unit 6.10.6 MSI Arithmetic and Logic Unit 6.10.7 Group-Carry Lookahead multiple ALU to be cascaded without ripple carry between 4 bit groups ( = 74 182 = carry lookahead generator) - 16 bit ALU using group carry lookahead 6.10.7 Group-Carry Lookahead 16 bit ALU using group carry lookahead 6.10.9 Adders in VHDL Concatenation operator to make A,B 8-bit to 9 bit S 6.10.9 Adders in VHDL 6.10.9 Adders in VHDL