Arsitektur Komputer Pertemuan – 15 Pemrosesan Paralel

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Arsitektur Komputer
Pertemuan – 15
Pemrosesan Paralel
© 2009 Fakultas Teknologi Informasi Universitas Budi Luhur
Jl. Ciledug Raya Petukangan Utara Jakarta Selatan 12260
Website: http://fti.bl.ac.id Email: [email protected]
Next Generation Network
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Multiple Processor Organization
1. Single instruction, single data stream
2. Single instruction, multiple data stream 3. Multiple instruction, single data stream 4. Multiple instruction, multiple data stream-
SISD
1. Single processor
2. Single instruction stream
3. Data stored in single memory
4. Uni-processor
SISD
SIMD
MISD
MIMD
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SIMD
1. Single machine instruction
2. Controls simultaneous execution
3. Number of processing elements
4. Lockstep basis
5. Each processing element has associated data memory
6. Each instruction executed on different set of data by different processors
7. Vector and array processors
MISD
1. Sequence of data
2. Transmitted to set of processors
3. Each processor executes different instruction sequence
4. Never been implemented
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MIMD
1. Set of processors
2. Simultaneously execute different instruction sequences
3. Different sets of data
4. SMPs, clusters and NUMA systems
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Taxonomy of Parallel Processor Architectures
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MIMD - Overview
General purpose processors
Each can process all instructions necessary
Further classified by method of processor communication
Tightly Coupled - SMP
Processors share memory
Communicate via that shared memory
Symmetric Multiprocessor (SMP)
Share single memory or pool
Shared bus to access memory
Memory access time to given area of memory is approximately the
same for each processor
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Tightly Coupled - NUMA
Nonuniform memory access
Access times to different regions of memroy may differ
Loosely Coupled - Clusters
Collection of independent uniprocessors or SMPs
Interconnected to form a cluster
Communication via fixed path or network connections
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Parallel Organizations - SISD
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Parallel Organizations - SIMD
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Parallel Organizations - MIMD Shared Memory
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Parallel Organizations - MIMD
Distributed Memory
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Symmetric Multiprocessors
A stand alone computer with the following characteristics
Two or more similar processors of comparable capacity
Processors share same memory and I/O
Processors are connected by a bus or other internal connection
Memory access time is approximately the same for each processor
All processors share access to I/O
Either through same channels or different channels giving paths to
same devices
All processors can perform the same functions (hence symmetric)
System controlled by integrated operating system
providing interaction between processors
Interaction at job, task, file and data element levels
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Multiprogramming and Multiprocessing
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SMP Advantages
1. Performance: If some work can be done in parallel
2. Availability: Since all processors can perform the same functions,
failure of a single processor does not halt the system
3. Incremental growth
User can enhance performance by adding additional
processors
4. Scaling
5. Vendors can offer range of products based on number of processors
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Block Diagram of Tightly Coupled Multiprocessor
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Organization Classification
Time shared or common bus
Multiport memory
Central control unit
Time Shared Bus
Simplest form
Structure and interface similar to single processor system
Following features provided
Addressing - distinguish modules on bus
Arbitration - any module can be temporary master
Time sharing - if one module has the bus, others must wait and may
have to suspend
Now have multiple processors as well as multiple I/O modules
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Symmetric Multiprocessor Organization
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Time Share Bus - Advantages
Simplicity
Flexibility
Reliability
Time Share Bus - Disadvantage
Performance limited by bus cycle time
Each processor should have local cache
Reduce number of bus accesses
Leads to problems with cache coherence
Solved in hardware - see later

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