Session 1.2

Report
IEEE P1687 Obstacle Course
John Potter
Sr. Principal Technologist
September 15, 2010
© 2010, ASSET InterTech, Inc.
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In this session, you will see ...
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What is IEEE P1687?
ICL and PDL
Example Network
Reset Architecture of an Instrument Network
Case Sensitivity, case SENSITIVITY, CASe …
Tracing : BSDL vs. P1687
Instrument Concurrency
Parameter Resolution
iApply Ambiguity
© 2010, ASSET InterTech, Inc.
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What is IEEE P1687?
• A proposed IEEE standard for the access of
embedded instruments
• Embedded Instruments can be for test, debug,
functional configuration, yield monitors, etc…
• Three important parts of the standard
• Hardware Architecture
• Hardware Architecture Description (ICL)
• Vector/Procedure Language (PDL)
© 2010, ASSET InterTech, Inc.
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ICL and PDL?
• ICL
• Instrument Connectivity Language
• Describe a 1687 Network (may include dynamic chains)
• Describe Instrument connection to the network
• Link Instrument vectors (PDL)
• PDL
• Procedure Description Language
• Describe behavioral functionality
• Create standard set of instrument interface operations
© 2010, ASSET InterTech, Inc.
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TAP SM
TAP IR
TCK
MBIST_1
TDI
TDO
BSDL
Description
bit[0]
L0_GWR
bit[1]
Gateway
Hierarchy Lev-0
© 2010, ASSET InterTech, Inc.
iMBIST_1
Gateway_1
LBIST_0
GWEN
iMBIST_0
Daisy-Chained
Instrument Interfaces
JTAG Regs
TMS
Static Signals
MBIST_0
TAP IR
With
GWEN
Instruction
Register Bits
P1687 Serial Instrument Network
Interface
Hierarchy Level-1
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iLBIST_0
Instrument
Reset Architecture of an Instrument Network
• Soft Reset – Scan in ResetValue of Update Cells
• Hard Reset – Global
• TLR
• Efficient and to the point
• Entire network affected
• Invoked by controlling process
• Hard Reset – Local
• Network Instruction Bit (NIB)
• Special, self-clearing network bit?
• Localized / Isolated / Targeted network reset
• iReset…Aye, Aye, Aye…AARRRGH Matey
© 2010, ASSET InterTech, Inc.
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Case Sensitivity of ICL and PDL
BSDL is Case In-sensitive
Verilog (chip design language) can be case sensitive
Potential exists to generate ICL from Verilog
Potential exists to generate Verilog from ICL
ICL AccessLink describes relationship to BSDL
• BSDL Entity Name
• Instruction Name
• Attachment to simulation
• If ICL is case sensitive, so goes PDL…
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• Case sensitivity is more about the content than the keywords
© 2010, ASSET InterTech, Inc.
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Tracing: BSDL vs. ICL
• BSDL
• One JTAG Instruction = One Test Data Register (TDR)
• All Data Register bits are in the scan path
• Scan Path has a fixed ScanLength
• ICL
• One JTAG Instruction = One or more TDRs
• Recommend PRIVATE Instruction
• Scan Path has dynamically changing ScanLength
• Scan Path depends on inferred connections
• Scan Path must be calculated after EACH UpdateDR
• Quiz: Where do bear tracks take you?
© 2010, ASSET InterTech, Inc.
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Bear Tracks Lead to…
© 2010, ASSET InterTech, Inc.
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Instrument Concurrency
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Run at the same time
Start at the same time
PDL Lock-Step
So, the instrument finished…
• Keep it in the network?
• Take it out of the network?
© 2010, ASSET InterTech, Inc.
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Parameters, Parameters, Parameters…
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Parameter Resolution
• Readability versus Reusability
• Readable: Explicit Port and Register sizing
• Generic: Parameterized Port and Register sizing
• Multi-Level Parameter Passing leads to obfuscated intent
• So goes parameters, so goes flattening the network
to resolve parameter references
• It looked good on paper…
© 2010, ASSET InterTech, Inc.
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iApply Ambiguity
• Writes are sticky – Reads are NOT sticky
• Random versus Literal ScanDR content
• Instruction Co-Dependence
• Discovering PDL intent matches ICL content
© 2010, ASSET InterTech, Inc.
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iApply Perspective – The Stage
RegA[3:0] = Sig_A, Sig_B, Sig_C, Sig_D
RegB[3:0] = Sig_E, Sig_F, Sig_G, Sig_H
TDI -> RegA -> RegB -> TDO
© 2010, ASSET InterTech, Inc.
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iApply Perspective – Act 1: The User (Register)
SDR 8 TDI (35) …;
iWrite RegA[3:0] 0b0011;
iWrite RegB[3:0] 0b0101;
iApply;
© 2010, ASSET InterTech, Inc.
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iApply Perspective – Act 1: The User (Signal)
SDR 8 TDI (35) …;
iWrite Sig_A 0b0;
iWrite Sig_B 0b0;
iWrite Sig_C 0b3;
iWrite Sig_D 0b3;
iWrite Sig_E 0b0;
iWrite Sig_F 0b1;
iWrite Sig_G 0b0;
iWrite Sig_H 0b1;
iApply;
© 2010, ASSET InterTech, Inc.
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iApply Perspective – Act 2: WG Member X
SDR 8 TDI (30) …;
SDR 8 TDI (35) …;
iWrite RegA[3:0] 0b0011;
iWrite RegB[3:0] 0b0101;
iApply;
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iApply Perspective – Act 3: Software Engineer
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
iWrite Sig_A 0b0;
iWrite Sig_B 0b0;
iWrite Sig_C 0b3;
iWrite Sig_D 0b3;
iWrite Sig_E 0b0;
iWrite Sig_F 0b1;
iWrite Sig_G 0b0;
iWrite Sig_H 0b1;
iApply;
© 2010, ASSET InterTech, Inc.
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TDI
TDI
TDI
TDI
TDI
TDI
TDI
TDI
(00)
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(20)
(33)
(30)
(34)
(30)
(35)
…;
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Good things come…
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PDL is WAY, WAY, WAY easier to write than SVF!!!
Allowance of Tcl finally gives true programmability via JTAG
Portable and Reusable Instrument “patterns”
Scheduling
© 2010, ASSET InterTech, Inc.
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In Summary …
• P1687 heading in a good direction
• P1687 needs some polish
• P1687 usage projects are fleshing out the complexity
© 2010, ASSET InterTech, Inc.
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