ADC

Report
ANALOG TO DIGITAL CONVERTERS
Stu Godlasky
Nikita Pak
James Potter
INTRODUCTION

What is an analog to digital converter (ADC)

Going from analog to digital

Types and properties of ADC
WHAT IS AN ANALOG TO DIGITAL
CONVERTER
 Converts
digital
an analog signal to discrete time
 Computers
, 1/0)
need digital. (On / Off , High / Low
GOING FROM ANALOG TO DIGITAL
Two step process
1)
Sampling – Measuring analog signal at uniform
time intervals
2)
Quantization – Assigning discrete
measurements a binary code (each sample will
have a binary number associated with it)

T1
T2
T3
T4
Example of
digital signal
from 3 bit ADC
010 010 011
ALIASING
Every analog signal has a frequency
 Nyquist Frequency (half sampling frequency)
 Aliasing occurs when signal above Nyquist
frequency

QUANTIZATION ERROR
Analog (infinite values) – Digital (finite values)
 Upon reconstruction of analog signal
 Increases as resolution decreases

Resolution - Q
EFSR - full scale voltage range
N = Number of discrete voltage intervals
N = 2k where k is the number of bits
QUANTIZATION ERROR
•Quantized signal only has values at midpoint of
voltage band
TYPES OF ANALOG TO DIGITAL
CONVERTERS
Dual Slope A/D Converter
 Successive Approximation A/D Converter
 Flash A/D Converter
 Delta – Sigma A/D Converter

DUAL SLOPE ANALOG TO DIGITAL
CONVERTER

Also referred to as an Integrating ADC
Integrator
DUAL SLOPE ANALOG TO DIGITAL
CONVERTER


Converts in two phases (ramp up / ramp
down )
Input voltage measurement not
dependant on integrator components
DUAL SLOPE ANALOG TO DIGITAL
CONVERTER
Pros



Conversion result is
insensitive to errors in the
component values
Fewer adverse affects
from noise
High accuracy
Cons
o Slow
o Accuracy is dependant
on the use of precision
external components
o Cost
SUCCESSIVE APPROXIMATION ANALOG TO
DIGITAL CONVERTER






DAC = Digital to Analog Converter
EOC = End of Conversion
SAR = Successive Approximation Register
S/H = Sample and Hold Circuit
Vin = Input Voltage
Vref = Reference Voltage
SUCCESSIVE APPROXIMATION ANALOG TO
DIGITAL CONVERTER




Uses an n-bit DAC and original analog results
Performs a bit by bit comparison of VDAC and Vin
If Vin > VREF / 2 MSB set to 1 otherwise 0
If Vin > VDAC Successive Bits set to 1 otherwise 0
SUCCESSIVE APPROXIMATION ADC
EXAMPLE
10 bit ADC
 Vin = 0.6 V
 Vref = 1V

N = 2n (n = number of bits)
N = 210 = 1024
Vref = 1V/ 1024
= 0.0009765625V (resolution)
SUCCESSIVE APPROXIMATION DIGITAL TO
ANALOG CONVERTER
Pros




Capable of high speed
and reliable
Medium accuracy
compared to other ADC
types
Good tradeoff between
speed and cost
Capable of outputting
the binary number in
serial (one bit at a
time) format.
Cons
o Higher resolution
successive approximation
ADCs will be slower
FLASH ANALOG TO DIGITAL CONVERTER
Also called a parallel ADC
 2N – 1 Comparators
 2N Resistors
 Control Logic (encoder)

FLASH ANALOG TO DIGITAL CONVERTER
Uses the resistors to divide reference voltage into
intervals
 Uses comparators to compare Vin and the reference
voltages
 Encoder takes the output of comparators and uses
control logic to generate binary digital output

FLASH ANALOG TO DIGITAL CONVERTER
Pros
 Very Fast (Fastest)
 Very simple operational
theory
 Speed is only limited by
gate and comparator
propagation delay
Cons
o Expensive
o Prone to produce
glitches in the output
o Each additional bit of
resolution requires twice
the comparators and
resistors
SIGMA-DELTA ANALOG TO DIGITAL
CONVERTER
 Input
over sampled, goes to integrator
 Integration compared with ground
 Iteration drives integration of error to
zero
 Output is a stream of serial bits
SIGMA-DELTA ANALOG TO DIGITAL
CONVERTER
Pros
 High resolution
 No need for precision
components
Cons
oSlow due to over
sampling
o Only good for low
bandwidth
COMPARISON OF ADCS
Type
Speed
(relative)
Cost
(relative)
Resolution
Dual Slope
Slow
Med
12-16
Flash
Very Fast
High
4-12
Successive
Approx
Medium –
Fast
Low
8-16
Sigma –
Delta
Slow
Low
12-24
ANALOG TO DIGITAL
CONVERTER APPLICATIONS
Nikita Pak
ANALOG TO DIGITAL CONVERTER
APPLICATIONS
Music recording
 Data acquisition/measurement devices

thermocouples
 digital multimeters
 strain gauges


Consumer Products
cell phones
 digital cameras

MUSIC RECORDING




A to D used to convert sound
pressure waves into discrete
digital signal (later, D to A used
to convert back to an electrical
signal for a speaker)
Saves a tremendous amount of
space
Ex. CD samples at 44.1 kHz
(Nyquist frequency = 22.05 kHz
is higher than human ear can
detect)
CD recording often done with
flash A to D
DATA ACQUISITION
Data acquisition: the
process of obtaining
signals from sensors that
measure physical
conditions
 Sensors give analog
voltage that must be
converted to work on a
computer
 Most National
Instruments DAQ’s use
successive approximation
A to D

MEASUREMENT DEVICES
Thermocouple: a junction of dissimilar metals
creates a voltage difference that is temperature
dependent
 Digital multimeter: converts signal to a voltage and
amplifies it for measurement
 More accurate than analog counterparts

MEASUREMENT DEVICES

Strain gauge: most common type
measures the change in
resistance as a metal pattern is
deformed
R
L
A
CONSUMER PRODUCTS
Cell phones: convert your voice into
a digital signal so it can be more
efficiently transmitted by
compressing the signal
 Digital camera ccd: absorbed
photons create charges that are
converted into a sequence of
voltages
 These voltages are converted to a
digital signal
 Both often use flash A to D

ADC ON YOUR MICROCONTROLLER
Input Pins
ADC Built-into
MC9S12C32
ADC IN BLOCK DIAGRAM
ATD 10B8C
Port AD
DETAILS OF ATD 10B8C
Analog-To-Digital
 Resolution: 8 or 10 Bits (manually chosen)
 8-Channel multiplexed inputs

Conversion time: 7 µs (for 10 bit mode)
 Optional external trigger
 “Successive approximation” type ADC

ATD 10B8C BLOCK DIAGRAM
ATD 10B8C BLOCK DIAGRAM
Reference Voltages
Results of Successive
Approximation
Source
Vsource
“Holds” Source Voltage
REGISTERS
AND
SETTING
James Potter
UP YOUR ATD10B8C
ADC REGISTERS
All information about registers found in
Chapter 8 of MC9S12C Family Reference Manual

8 Result Registers
 6 Control Registers
 2 Status Registers
 2 Test Registers
 1 Digital Input Enable Register
 1 Digital Port Data Register

RESULT REGISTERS
RESULT REGISTERS
8 registers,
Each with
High and low byte
RESULT REGISTERS:
LEFT-JUSTIFIED (DEFAULT)

High Byte

Low Byte
RESULT REGISTERS:
RIGHT-JUSTIFIED

High Byte

Low Byte
CONTROL REGISTERS
CONTROL REGISTERS:
ATDCTL2
CONTROL REGISTERS:
ATDCTL2
CONTROL REGISTERS:
ATDCTL3
CONTROL REGISTERS:
ATDCTL3
CONTROL REGISTERS:
ATDCTL4
CONTROL REGISTERS:
ATDCTL4
CONTROL REGISTERS:
ATDCTL5
CONTROL REGISTERS:
ATDCTL5
CONTROL REGISTERS:
ATDCTL5
SINGLE CHANNEL (MULT = 0)
SINGLE CONVERSION (SCAN = 0)
ATDDR7
ATDDR6
7
6
5
4
3
2
1
0
ATDDR5
ATDDR4
ATDDR3
Port AD
Result
Register
Interface
ATD Converter
ATDDR2
ATDDR1
ATDDR0
SINGLE CHANNEL (MULT = 0)
CONTINUOUS CONVERSION (SCAN = 1)
ATDDR7
ATDDR6
7
6
5
4
3
2
1
0
ATDDR5
ATDDR4
ATDDR3
Port AD
Result
Register
Interface
ATD Converter
ATDDR2
ATDDR1
ATDDR0
MULTIPLE CHANNEL (MULT = 1)
SINGLE CONVERSION (SCAN = 0)
ATDDR7
ATDDR6
7
6
5
4
3
2
1
0
ATDDR5
ATDDR4
ATDDR3
Port AD
Result
Register
Interface
ATD Converter
ATDDR2
ATDDR1
ATDDR0
SINGLE CHANNEL (MULT = 1)
CONTINUOUS CONVERSION (SCAN = 1)
ATDDR7
ATDDR6
7
6
5
4
3
2
1
0
ATDDR5
ATDDR4
ATDDR3
Port AD
Result
Register
Interface
ATD Converter
ATDDR2
ATDDR1
ATDDR0
STATUS REGISTERS
STATUS REGISTER 0:
ATDSTAT0
STATUS REGISTER 0:
ATDSTAT0
STATUS REGISTER 1:
ATDSTAT1
SETTING UP YOUR ATD10B8C
SETTING UP THE ATD

Step 1: Power-up the ATD and define settings in
ATDCTL2
ADPU = 1 powers up the ATD
ASCIE = 1 enables interrupt


Step 2: Wait for ATD recovery time (~ 20μs) before
proceeding
Step 3: Set number of successive conversions in
ATDCTL3
S1C, S2C, S4C, S8C determine number of conversions (see Table 8-4)
SETTING UP THE ATD

Step 4: Configure resolution, sampling time, and ATD
clock speed in ATDCTL4
PRS0, PRS1, PRS2, PRS3, PRS4 set sampling rate (see Table 8-6)
SRES8 sets resolution to 8-bit (= 1) or 10-bit (= 0)

Step 5: Configure starting channel, single/multiple
channel, SCAN and result data signed or unsigned in
ATDCTL5
CC, CB, CA determine input channel (see Table 8-12)
MULT sets single (= 0) or multiple (= 1) inputs
SCAN sets single (= 0) or continuous (= 1) sampling
DJM sets output format as left-justified (=0) or right-justified (=1)
DSGN sets output data as unsigned (=0) or signed (=1)
THANK YOU

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