ch7-3

Report
Chapter 7, part 3:
Hardware/Software Co-Design
High Performance Embedded
Computing
Wayne Wolf
High Performance Embedded Computing
© 2007 Elsevier
Topics
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Multi-objective optimization.
Co-synthesis for control.
Co-synthesis for caches.
Co-synthesis for reconfigurable platforms.
Hardware/software co-simulation.
© 2006 Elsevier
Multi-objective optimization
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Operations research provides notions for
optimization functions with multiple
objectives.
Pareto optimality: optimal solution cannot be
improved without making something else
worse.
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GOPS
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Feasibility factor
computed from
throughput factors.
Upper-bound
throughput for RMS:
Upper-bound
throughput for EDF:
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Upper bound feasibility
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Upper-bound feasibility
tests:
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Lower bound feasibility test
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Lower bound:
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Feasibility factor
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Feasibility factor lP:
Use feasibility factor to prune the search space and
as an optimization objective.
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Genetic algorithms
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Modeled as:
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Genes = strings of symbols.
Mutations = changes to strings.
Types of moves:
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Reproduction makes a copy of a string.
Mutation changes a string.
Crossover interchanges parts of two strings.
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MOGAC
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Technology tables characterize hardware
components.
Genetic model:
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Processing element allocation string lists all PEs
and types.
Task allocation string shows assignment of tasks
to PEs.
Link allocation task maps communication to links.
IC allocation string maps tasks to chips.
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MOGAC optimization procedure
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Forms initial solution.
Repeats
evolve/evaluate cycle.
Evaluation determines
noninferior solutions.
Some noninferior
solutions may not
survive evolution.
Clusters solutions to
reduce run time.
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[Dic98] © 1998 IEEE
MOGAC constraints
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nis(x): noninferior solutions in x.
dom(a,b) = 1 if a is not dominated by b.
Cluster rank:
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Energy-aware task scheduling
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Yang et al. schedule multiprocessors for
energy.
Combine design-time and runtime:
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At design time, scheduler evaluates
scheduling/allocation choices; optimizes with
genetic algorithms; generates table.
At run time, heuristics use the table to choose
best scheduling/allocation pattern.
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Co-synthesis for wireless
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Wireless systems are bandwidth and energy
limited.
COWLS uses parallel recombinative
simulated annealing.
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Ranked by communication time, computation
time, utilization.
Scheduling influences both power
consumption and timing.
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Slack determines idle time.
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Control and I/O synthesis
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Control finite-state machine (CFSM) model
describges control-dominated systems.
Event-driven model.
Finite, non-zero, unbounded reaction times.
Implementations:
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Hardware is logic guarded by latches.
Software is synthesized from s-graph that models control
flow graph.
Can be used as an intermediate representation for
Esterel, etc.
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Modal process model
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Chou et al. use modal models:
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I/O behavior depends on current mode and on
inputs.
Abstract control types define control
operations with known properties.
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Interface synthesis
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Chou et al. represent I/O as control flow
graphs.
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Generate tasks, allocate I/O ports, split wide-word
operations, use memory mapped I/O where
ncessary, generate I/O sequencer.
Daveau et al. synthesize communication by
allocating operations to units in a library.
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Communication unit must provide requred
services, use the right protocol, and run at the
required data rate.
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Cache modeling for co-synthesis
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Cache state affects
task execution time.
Li and Wolf used twostate model for
processes in cache:
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One time if in cache.
Another time if not in
cache.
This model is more
abstract than cache line
model.
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[Li99] © 1999 IEEE
Co-synthesis with caches
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System cost:
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Hierarchical scheduling
algorithm:
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Schedule tasks (>=
process) over hyperperiod.
Refine schedule by moving
processes within a task.
Dynamic urgency models
how process uses cache:
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Wuytack et al.
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1.
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Methodology for dynamic memory management:
Define application using abstract data types.
Refine ADTs into concrete data structures.
Virtual memory divided among several memory
managers.
Spit virtual memory segments into groups to
parallelize data accesses.
Order background memory accesses to optimize
bandwidth.
Allocate physical memories.
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Co-synthesis for reconfigurable systems
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FPGA fabric can hold
different accelerators at
different times.
Combinations of
accelerators may be
limited.
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Must take floorplan into
account.
Schedule must take
reconfiguration time,
energy into account.
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CORDS
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CORDS uses evolutionary algorithms similar
to MOGAC.
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Adds reconfiguration delay to costs based on
current schedule state.
Dynamic priority of task depends on slack +
reconfiguration delay.
Increases dynamic priority of tasks with low
reconfiguration time to group together several
reconfigurations and save energy.
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Nimble
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Performs fine-grained
partitioning for instructionlevel parallelism.
Platform described in
architecture description
language.
Program represented as
control flow graph.
Selects interesting parts of
loops by analyzing control
dependence graph.
[Li00] © 2000 IEEE
© 2006 Elsevier
Hardware/software co-simulation
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Must connect models with
different models of
computation, different time
scales.
Simulation backplane
manages communication.
Becker et al. used PLI in
Verilog-XL to add C code
that communicates with
software models, UNIX
networking to connect
hardware simulator.
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Mentor Graphics Seamless
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Hardware modules described using standard
HDLs.
Software can be loaded as C or binary.
Bus interface module connects hardware
models to processor instruction set simulator.
Coherent memory server manages shared
memory.
© 2006 Elsevier

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