Unit 6 PowerPoint Slides

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EET 1131 Unit 6
Exclusive-OR and Exclusive-NOR
Gates
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
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
Read Kleitz, Chapter 6.
Do Unit 6 e-Lesson.
Homework #6 and Lab #6 due next
week.
Quiz next week.
The XOR Gate
A
B
X
A
B
=1
X
The XOR gate produces a HIGH output only when the
inputs are at opposite logic levels. The truth table is
Inputs
Output
A
B
X
0
0
1
1
0
1
0
1
0
1
1
0
The XOR operation is written as X = AB + AB.
Alternatively, it can be written with a circled plus sign
between the variables as X = A + B.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The XOR Gate
A
B
X
A
B
=1
X
Example waveforms:
A
B
X
Notice that the XOR gate will produce a HIGH only when exactly one
input is HIGH.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Fixed Function Logic
Some common gate configurations are shown.
VCC
VCC
14 13 12 11 10 9
1
2
3
4
5
6
8
7
GND
VCC
14 13 12 11 10 9
1
2
3
'00
6
7
GND
2
3
4
5
6
8
7
GND
1
2
3
4
5
6
8
7
GND
'27
5
6
8
7
GND
5
6
7
GND
2
3
4
'30
1
2
3
5
6
8
7
GND
2
3
4
5
6
6
7
GND
8
7
GND
14 13 12 11 10 9
1
2
3
4
5
6
8
7
GND
'21
VCC
14 13 12 11 10 9
1
5
VCC
14 13 12 11 10 9
1
4
8
'08
VCC
14 13 12 11 10 9
1
4
14 13 12 11 10 9
'20
VCC
14 13 12 11 10 9
4
3
'11
VCC
3
2
VCC
14 13 12 11 10 9
'10
2
1
8
'04
VCC
14 13 12 11 10 9
1
5
VCC
14 13 12 11 10 9
' 02
VCC
1
4
8
2
3
4
'32
5
6
8
7
GND
14 13 12 11 10 9
1
2
3
4
5
6
8
7
GND
'86
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The XNOR Gate
A
B
X
A
B
=1
X
The XNOR gate produces a HIGH output only when the
inputs are at the same logic level. The truth table is
Inputs
Output
A
B
X
0
0
1
1
0
1
0
1
1
0
0
1
The XNOR operation can be written as X = AB + AB or as
X = A + B.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The XNOR Gate
A
B
X
A
B
=1
X
Example waveforms:
A
B
X
Notice that the XNOR gate will produce a HIGH when both inputs are the
same. This makes it useful for comparison functions.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Applications of XOR and XNOR
Gates
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Three common applications:
1.
2.
3.
Comparators
Controlled inverters
Parity generation and checking
Convention for Multi-Bit Strings
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When dealing with multi-bit binary
strings, we use subscripts to refer to
the individual bits in the string.
The least significant bit (LSB) always
gets the smallest subscript, which may
be either 1 or 0.
Example: In a four-bit string A, the
bits may be labeled either
A4A3A2A1
or
A3A2A1A0
Application #1: Comparator
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A comparator compares two strings of bits
to see whether they are equal to each
other:
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Example: if string A = 0101 and string B = 0100,
then A≠ B.
Next slide shows how to build a 4-bit
comparator from XNOR gates.
Comparator Circuit (Book’s Fig. 6-14)
Application #2: Controlled Inverter
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A controlled inverter takes an input string
and, depending on the logic level on a
control line, either



Leaves the string unchanged or
Inverts each bit in the string
Next slide shows how to build an 8-bit
controlled inverter from XOR gates.
Controlled Inverter (Book’s Fig. 6-15)
Application #3: Parity Checking
Parity checking is a method of error detection for
simple transmission errors involving one bit. A parity bit
is an “extra” bit attached to a group of bits to force the
total number of 1’s to be either even (even parity) or
odd (odd parity).
The ASCII character for “a” is 1100001 and for “A” is
1000001. What is the correct bit to append to make both of
these have odd parity?
The ASCII “a” has an odd number of bits that are equal to 1;
therefore the parity bit is 0. The ASCII “A” has an even
number of bits that are equal to 1; therefore the parity bit is 1.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Parity Generators
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To implement parity checking, we need
circuitry on the sending end that
generates the parity bit for each group
of bits being sent. This circuitry is
called a parity generator.
Next slide shows how to build 4-bit
even or odd parity generators.
Parity Generators (Book’s Fig. 6-9)
Parity Checkers
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On the receiving end, we need circuitry
that checks the data bits and parity bit
as they’re received to decide whether an
error has occurred during transmission.
This circuitry is called a parity checker.
Next slide shows how to build a 4bit-plus-parity even parity checker.
Parity Checker (Book’s Fig. 6-11)
A Parity Generator/Checker Chip
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74280 Nine-bit Parity Generator/Checker
Most chips we’ve studied have been SSI
(small-scale integration) chips containing
fewer than 10 gates that are not connected
to each other.
The 74280 is an MSI (medium-scale
integration) chip. Instead of containing a
few disconnected gates, it contains about 45
gates connected internally on the chip to
perform a specific function.
Parity System (Book’s Fig. 6-13)
Parity Generator/Checker Chip
The 74280 can be used to generate a parity bit or to check
an incoming data stream for even or odd parity.
Checker: The 74280 can test codes with up to
9 bits. The even output will be HIGH if the
data lines have even parity; otherwise it will
be LOW. Likewise, the odd output will be
HIGH if the data lines have odd parity;
Data
otherwise it will be LOW.
inputs
Generator: To generate even parity, the parity
bit is taken from the odd parity output. To
generate odd parity, the output is taken from
the even parity output.
(8)
(9)
(10)
(11)
(12)
(13)
(1)
(2)
(4)
A
B
C
D
E
F
G
H
I
(5)
(6)
S Even
S Odd
74280
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Printing from Our Oscilloscopes
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You can print the oscilloscope screen by
pressing the PRINT button.
There’s a delay of about 40 seconds before
the page will print, so be patient.
Only one oscilloscope can print at a
time, or else the printer gets confused
and prints hundreds of pages.
Please shout “Printing!” before you press the
PRINT button, and make sure that you don’t
print while someone else is waiting for their
page to print.

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