Report

Impact of Adaptive Voltage Scaling on Aging-Aware Signoff Tuck-Boon Chan, Wei-Ting Jonas Chan and Andrew B. Kahng VLSI CAD LABORATORY, UC San Diego Outline • • • • Introduction: BTI Aging and AVS Signoff Problem Observations and Proposed Heuristics Experimental Results 1 Outline • • • • Introduction: BTI Aging and AVS Signoff Problem Observations and Proposed Heuristics Experimental Results 2 Intro: Bias Temperature Instability (BTI) |ΔVth| increases when device is on (stressed) |ΔVth| is partially recovered when device is off (relaxed) NBTI: PMOS PBTI:NMOS |Vgs| ON OFF ON OFF time Device aging (|ΔVth|) accumulates over time [VattikondaWC06] 3 Intro: Adaptive Voltage Scaling (AVS) • Accumulated BTI higher |ΔVth| slower circuit • AVS can be used to compensate for performance degradation Circuit On-chip aging monitor Circuit performance Without AVS With AVS target time Voltage regulator Circuit performance Closed-loop AVS Vdd time 4 Outline • • • • Introduction: BTI Aging and AVS Signoff Problem Observations and Proposed Heuristics Experimental Results 5 Problem: Signoff Corner Definition • Timing signoff: ensure circuit meets performance target under PVT variations & aging • Conventional signoff approach: – Analyze circuit timing at worst-case corners – Fix timing violations, re-run timing analysis • With BTIaging agingand andAVS, AVS, what is the Vvoltage worst-cast With BTI the worst-case corner is not dd of the corner obviousfor timing analysis? Vlib for circuit performance estimation Min Vdd Min Vdd VBTI for aging Max estimation Vdd Slowest circuit Less aging Max Vdd ? Slowest circuit Too Worst-casepessimistic aging Not applicable (Optimistic) Faster circuit Worst-case aging ? 6 Derated Library Characterization & AVS • VBTI = Voltage for BTI aging estimation • Vlib = Voltage for circuit performance estimation (library characterization) • VBTI and Vlib are required in signoff • Good VBTI and Vlib selection should consider expected BTI + AVS • Aging and Vfinal are unknowns before circuit implementation Step 1 VBTI |Vt| Vlib ? Vfinal Step 2 Derated library Step 3 Circuit implementation and signoff BTI degradation and AVS circuit 7 Library Characterization for AVS • VBTI = Voltage for BTI aging estimation • Vlib = Voltage for circuit performance estimation final lib (library BTI characterization) • VBTI and Vlib are required in signoff No obvious • VBTI and Vlib depend on aging during AVS guideline to define • Aging and Vfinal are unknowns before VBTI and Vlib circuit implementation Inconsistency among V , V & V • What is the design overhead when timing libraries are not properly characterized? • What are guidelines to define BTIand Step 1 Step 2 Step 3 AVS-aware Circuit V |V | signoff corners that Derated implementation and library guarantee timing correctness with V signoff little design overhead? BTI degradation V circuit ? and AVS BTI t lib final 8 Previous Works • There are many previous works on BTI + AVS – [Basoglo10] [Kumar11] [Mintarno11] … – No discussion of signoff for a circuit with BTI + AVS • Previous works assume a circuit is signed off with timing libraries without BTI degradation • Then analyze BTI + AVS effects on circuit timing – If circuit timing fails to meet requirements design iteration + signoff longer design time – An example of timing failure: AVS requires Vdd > maximum allowed voltage to compensate aging 9 Outline • • • • Introduction: BTI Aging and AVS Signoff Problem Observations and Proposed Heuristics Experimental Results 10 “Chicken and Egg” Loop • “Chicken and egg” loop in signoff – Derated library characterization is related to BTI + AVS – AVS affected by circuit implementation • Timing constraints, critical paths, etc. – Circuit is affected by library characterization Vfinal Circuit Vlib , VBTI Derated Libraries 11 Observation #1 • BTI is a “front-loaded” phenomenon • 50% BTI aging happens within the 1st year of circuit lifetime (total lifetime = 10 years) [Chan11] Vfinal ≈70% Vdd increment in 1 year (remaining 30% over 9 years) • Most Vdd increment happens in early lifetime • Gap between Vdd and Vfinal reduces rapidly 12 Heuristics #1 • Model BTI degradation with Vfinal throughout lifetime – Aging of a flat Vfinal ≈ aging of an adaptive Vdd – But slightly pessimistic VBTI = Vlib ≈ Vfinal NBTI Vdd PBTI time 13 Vfinal Estimation • Problem: Vfinal is not available at early design stage (design has not been implemented) • Vfinal = Vdd @ end of life (to compensate BTI aging) – Gates along critical path ? – Timing slack at t = 0 ? – Circuit activity (BTI aging) ✔ • BTI aging depends on circuit activity – Assume DC or AC stress in derated library characterization 14 Observation and Heuristic #2 • Observation #2: Vfinal is not sensitive to gate types • Heuristic #2: use average Vfinal of different gate types – Vfinal is a function of timing slack – Assume timing slack = 0 10mV 15 Proposed Library Characterization Flow Obtain Vheur (average of standard cells) • Heuristic #2: obtain Vheur by averaging Vfinal of different cells Obtain derated library with VBTI = Vlib = Vheur • Heuristic #1: use a “flat” Vheur to estimate BTI degradation Signoff circuit with derated library 16 Outline • • • • Introduction: BTI Aging and AVS Signoff Problem Observations and Proposed Heuristics Experimental Results 17 A Reference Signoff Flow • Basic idea: keep a consistent VBTI , VLIB and Vdd throughout circuit lifetime • Signoff flow: – Estimate aging at each time step – Update circuit timing and Vdd – Repeat until t = tfinal – Modify circuit and start over if Vfinal > maximum allowed voltage • No overhead in timing analysis, but very slow Many STA runs and library Vstep: AVS voltage step Vfinal: converged voltage 18 Technology and Benchmark Circuits • NANGATE library with 32nm PTM technology • Signoff for setup time violation • Temperature = 125C • Process corner = slow NMOS and PMOS • BTI degradation = {DC, AC} Supply voltages Circuit C5315 c7552 AES Frequency (GHz) 1.38 1.25 0.89 MPEG2 1.05 Vmax Vinit Vheur1 (DC) 1.05V Vheur1 (AC) Vheur2 (DC) Vheur2 (AC) 0.95V 0.90V 0.97V 0.95V 0.93V 19 Experiment Setup • Characterize different derated libraries • Evaluate impact of library characterization • Seven testcases 1 : VBTI = Vlib = Vinit Ignore AVS 2 : Most pessimistic derated library 3 : VBTI = Vlib = Vmax Extreme corner for AVS 4 : VBTI = Vfinal Do not overestimate aging but ignores AVS 5 : No derated library (reference) 6 : Proposed method with α=0 7 : Proposed method with α=0.03 Case Vlib(V) 1 Vinit 2 Vinit VBTI (V) Vinit Vmax 3 Vmax Vmax 4 Vinit 5 N/A Vfinal N/A 6 7 Vheur1 Vheur1 Vheur2 Vheur2 20 Results for DC Scenario Good corners Optimistic signoff corner • AVS increases supply voltage aggressively to compensate aging • Consume more power • May fail to meet timing if desired supply voltage > Vmax 1 : VBTI = Vlib = Vinit Ignore AVS 2 : Most pessimistic derated library 3 : VBTI = Vlib = Vmax Extreme corner for AVS 4 : Vbti = Vfinal Do not overestimate aging but ignores AVS 5 : No derated library (reference) 6 : Proposed method with α=0 7 : Proposed method with α=0.03 Pessimistic signoff corner • Ovestimate aging and/or underestimate circuit performance • Large area overhead 21 Results for AC Scenario Good corners • Similar results as in the DC scenario • Design overheads due poorly characterized libraries (#1 to #4) are smaller compared to the DC scenario 22 Power vs. Area for All Designs • Overlay all data points (4 designs x {DC, AC}) Circuit signed off using our derated libraries Circuit signed off using other derated libraries “Knee” point for balanced area and power tradeoff 23 Conclusions • Voltage for aging estimation (VBTI), library characterization (Vlib) and operation (Vfinal) are inconsistent • Poorly-characterized libraries lead to circuit area or power overheads • We propose a flow to characterize a derated library – Heuristic #1: approximate Vlib = VBTI ≈ Vfinal – Heuristic #2: use replica circuits to estimate Vfinal • Circuits implemented with our derated libraries have similar area and power as those implemented from a reference flow 24 Future Works • A comprehensive aging- and AVS-aware library characterization including PVT corners • Consider hold time violation due to degradation in clock distribution network • Re-examine signoff corners with AVS – Do we still need to signoff at the worst-case corners? 25 Thank you! 26 Implementation of Reference Signoff Flow • Create new libraries for eachConventional STA time step is too slow • Alternative implementation • Pre-characterize libraries for different VBTI, Vlib • Interpolate power, leakage, and delay using the pre-characterized libraries 27 Interpolation Results • Compare values from actual libraries vs. interpolation • Interpolation errors are negligible 28 BTI Model • Use BTI model in [Vattikonda06] • Fitting parameters are characterized with published data in [Zafar06] NBTI [Zafar06] 29 BTI Aging and AVS NBTI and PBTI degrade circuit performance over lifetime Two variables of aging severity • Supply voltage: » Higher VDD speeds up BTI aging • Activity: » Stressed: |Vth| of transistor increases when it is on » Relaxed: Part of the |Vth| increment is recovered when transistor is off Degradation vs. Operation Modes Degradation • • Max VDD Max VDD Max VDD Adaptive VDD Adaptive VDD Signal probability AC Adaptive VDD DC Transistor stress time 30 Braking the Loop • VBTI = Vlib = Vfinal to avoid overly pessimistic or optimistic • Heuristic: estimate VBTI, Vlib with circuit replica Circuit Replica Vlib , VBTI Derated Libraries Vlib= VBTI ≈ Vfinal Vfinal Circuit 31