SPI Top - vlsi-spi

Report
Serial Peripheral Interface
Final Project Presentation
27.12.2011
Presented by:
• Omer Shaked
• Beeri Schreiber
Project Requirements
1. Implement SPI Master and SPI Slave cores (VHDL)
2. Implement Master and Slave hosts (VHDL)
3. Verify the entire design (SystemVerilog)
SPI In General
• Serial data link standard
• Operates in full duplex mode
• Devices communicate in master/slave mode
• Single master, multiple slaves
• The master initiates the data frame
SPI In General (Cont.)
• The interface is consumed of four signals:
• SPI_CLK: Serial Clock (output from master)
• SPI_MOSI: Master Output, Slave Input
• SPI_MISO: Master Input, Slave Output
• SPI_SS: Slave Select (output from master).
SPI In General (Cont.)
• The master configures the clock polarity and phase
Wishbone In General
• Please add general description of WB
Implementation Stages
Unit Level
• Design of SPI Master and SPI Slave cores
• Design internal blocks of master and slave hosts
• SPI Master and SPI Slave individual Test Benches
Implementation Stages
Top Level
• Integration of SPI cores
• Integration of master and slave hosts
• SPI top test bench
• Top architecture test bench
SPI Core Design
• Four main interfaces:
SPI Core
CFG interface
• Generic word length
• Generic number of slaves
SPI Interface
FIFO Interface
Received Data Interface
Slave
Host
RAM
Interface
SPI
Slave
Interface
Master
Host
SPI
Master
Interface
Wishbone
Slave
Interface
Top Architecture Design
• Master host implements Wishbone slave interface
• Hosts communicate via SPI
• Slave host implements RAM interface
RAM
Master Host Design
Master Host
Wishbone
Slave
Controller
M.P.
Decoder
Checksum
Enc.
RAM
M.P.
Encoder
‘0’
FIFO
SPI
Master
SPI Interface
Dec.
RAM
MUX
Wishbone Interface
Checksum
Slave Host Design
Slave Host
Slave Host Controller
SPI
Slave
Dec.
RAM
RAM
Controller
Registers
Checksum
FIFO
M.P.
Encoder
Enc.
RAM
RAM Interface
SPI Interface
M.P.
Decoder
Read
MUX
Checksum
R
A
M
Verification Plan
• Basic block-level VHDL TBs during design stage
• SystemVerilog TBs
• SPI Master
• SPI Slave
• SPI Top
• Architecture Top
Verification Plan (Cont.)
• Main verification principles
• Use of randomly generated values
• Coverage collection
• Automatic scoreboarding
• SPI cores – include possible edge cases
• Top architecture – only basic functionality
SPI Master Test Bench
Test Name
5
Status
Scoreboard
Normal burst
All CPOL, CPHA configurations
2
3
Generator
All SPI clock frequencies
and
SPI Master
Driver
Reset
(DUT)
Forbidden Configuration
Receiver
Generator
and
Driver
SPI Interface
7
FIFOI interface
1
4
Receiver
CFG interface
FIFO Error
6
CFG_DUT
Illegal SPI Clock Frequencies
+
+
SPI Slave Test Bench
Test Name
Status
6
Normal burst
Scoreboard
All CPOL, CPHA configurations
1
Interrupt
7
CFG_DUT
SPI Interface
FIFOI interface
8
GeneratorMax SPI clock frequency
and
Reset
SPI Slave
Driver
(DUT)
Configuration during transmission
2
Receiver
CFG interface
Timeout
4
3
Generator
SPI Master
BFM
5
Receiver
SPI Top Test Bench
Test Name
Status
5
Normal burst
+
All CPOL, CPHA configurations
+
Scoreboard
7
DUT
Different SPI clock frequencies
+
1
3
SPI Slave1
SPI Slave2
SPI Slave3
CFG interface
CFG interface
6
CFG_DUT
FIFOI interface
SPI Slave0
SPI Interface
Receiver
SPI Interface
2
FIFOI interface
Generator Max SPI clock frequency
and
Driver
Generics
SPI Master
+
+
Generator
and
Driver
4
Receiver
Top Test Bench (UVM 1.1)
UVM_TEST
Test Name
UVM_ENV
1
5
DUT
All CPOL, CPHA configurations
Sequencer
WBS
Agent
All burst lengths
Status
3
All SPI clock frequencies
Monitor
Driver
Burst length exceeds RAM address
2
4
Transaction interrupted
Scoreboard
Reset in middle of transaction
Master
Host
SPI
I/F
Slave
Host
External
RAM
SV Verification Summary
• Total of 8 bugs were found
• SPI Master – 2
• SPI Slave---------------------------------------------------------------------------------------------------–3
Covergroup
Metric Goal/ Status
At Least
• Top – 2 ---------------------------------------------------------------------------------------------------COVERGROUP COVERAGE:
TYPE /top/master_host_monitor/cov_trans
100.0%
100 Covered
Coverpoint cov_trans::length
100.0%
100 Covered
Coverpoint cov_trans::init_addr
100.0%
100 Covered
Coverpoint cov_trans::div_factor
100.0%
100 Covered
Coverpoint cov_trans::cpol_cpha
100.0%
100 Covered
CLASS master_host_monitor
TOTAL COVERGROUP COVERAGE: 100.0% COVERGROUP TYPES: 1
• Reached 100 % coverage rate for all TBs
Summary & Conclusions
• A lot more than the original project
• Well-organized development methodology
• Relatively fast completion of the project
• Very enjoyable and fruitful
The End
Thanks to both of our supervisors !

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