Lecture 2

ECE 506
Reconfigurable Computing
Lecture 2
Reconfigurable Architectures
Ali Akoglu
Early Work
° How is it possible that a hardware device, whose
structure is
• normally fixed at fabrication time
• cannot be changed anymore during the lifetime,
• can be readapted at run-time to dynamically match the
application requirements?
° Historical perspective
° FPGA technology
Early Work: Gerald Estrin- FixPlus Machine 1959
° Introduced the concept of reconfigurable computing.
° The Fix-Plus Machine published in 1960, defines the
concept of reconfigurable computing paradigm.
° “The economic feasibility of the system is based on
utilization of essentially the same hardware in a variety of
special purpose structures. This capability is achieved by
programmed or physical restructuring of a part of the
Early Work
• A variable part (V) consists of
various digital substructures
that can be reorganized in
problem-oriented special
purpose configurations.
• problem-specific optimized
functional units (trigonometric
functions, logarithm,
exponentials, n-th power,
roots, complex arithmetic,
hyperbolic, matrix operation).
• Speed gain over IBM7090 (2.5
to 1000) for accelerating
Eigenvalues computation of
Early Work
four amplifiers and
associated input logic for
signal inversion,
amplification, or high-speed
ten diodes and four
output drivers and is
for combinatorial
The basic building blocks of Fix-Plus Machine
Early Work
° The basic block modules inserted into any of 36 positions
on a motherboard that provides the functionality for a
given application.
° The connection between the modules is established
through a wiring harness
° Function Reconfiguration means changing some modules
° Routing Reconfiguration means changing parts of the
wiring harness
Manual Reconfiguration
Programmable Logic Devices
° Fact: A Boolean function can be written as a sum of
products (AND/OR, NOR/NAND)
° Result:
• Programmable Logic Array (PLA) and Programmable Array Logic (PAL)
• Unlike a logic gate, which has a fixed function, a PLD has an undefined
function at the time of manufacture.
• Before the PLD can perform in a circuit it must be programmed.
° The first programmable logic devices were produced by
the Advanced Micro Devices (AMD) corporation.
° The PLD business split from AMD under the name Vantis,
and was acquired by Lattice Semiconductor in 1999.
Programmable Logic Array
° Introduced in 1975, the most user-configurable of the
traditional two-level programmable logic devices
° In Boolean terms, this means a number of AND gates
whose outputs feed into a large OR gate that drives one
° By selecting which inputs drive each AND gate, and
which AND gates drive the OR gate, any Boolean function
can be created.
Unprogrammed device
Programmed device
° Unwanted connections are
° PAL: AND array is programmable, but OR array is fixed
during fabrication.
• OR array has access to only subset of product terms.
Programmed PAL
° 4 product terms per
each OR gate
Limitation of PALs and PLAs
° Low capacity and speed
• size of the plane grows too quickly
• n times the number of inputs and outputs requires nxn as much chip
area → too costly
• logic gets slower as number of inputs to AND array increases
° Available in small sizes, equivalent to a few hundred logic
° Solution:
• Complex Programmable Logic Device
• multiple PLDs with a relatively small (fast) programmable interconnect
• less general than a single large PLD, but we can use software to
partition our design into smaller PLD blocks
Complex Programmable Logic Device
Complex Programmable Logic Device
° Hierarchical design against size explosion of PLAs
• Combinational logic with Flip Flops (registered output)
• Organized into logic blocks connected in an interconnect matrix
• Usually enough logic for simple counters, state machines, decoders, etc.
° Non-volatile!
• Programming kept on power
• Functions available instantly
on system power up
• Hard to steal stored design
• CPLDs are used in many
systems for configuration of
the main reconfigurable
device at start up.
Xilinx CoolRunner II CPLD
° PLA and Macrocell combination
° 1.8V device, estimated power consumption of less than
100 micro amps
° Up to 12,000 gates, 512 MacroCells
Complex Programmable Logic Device
° Contains from 10-1000 macrocells
° Each macrocell is equivalent to around 20 gates
° Support up to 200 I/O pins
° The key resource in a CPLD is the programmable
• Tradeoff between space for macrocells and space for interconnect
° Introduced in 1985 by Xilinx
° Similar to CPLDs
° A function to be implemented in FPGA
• Partitioned into modules , each implemented in a logic block.
• Logic blocks connected with the programmable interconnection.
FPGA Technology
° 1) Antifuse-based
• Realization of interconnections
° 2) Memory-based.
• realization of interconnections and computation
• SRAM, EEPROM and Flash

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