Printed Circuit Board Design - IEEE Concordia

Printed Circuit Board Design
IEEE Concordia Electronics Workshop
Presented by Marc-Alexandre Chan
Concordia University, room EV 2.184 – 19 November 2014
Photo by Christian Taube, CC-BY-SA 2.5.
Workshop Overview
Why PCBs?
Design Process
– Component Selection
Board, components &
3. Design Process
– Positioning
– Routing Techniques
– Ground/Power Planes
– Fabrication Restrictions
Component selection,
positioning, routing,
power & ground,
Advanced Design
Design your own!
– High-Frequency Circuits
– Internal Layers
Power & Ground
– External Connections
Workshop Overview
Why PCBs?
Board, components & software
3. Design Process
Component selection, positioning, routing, power &
ground, fabrication
Design your own!
4. Some advanced considerations
External connectors, multi-layer boards, high frequency
PCB Basics
Why PCBs?
Limited alternatives
– Breadboard, perfboard, chassis mount
Custom designed for each circuit
High flexibility
Compact (high density)
Protective solder mask
20+ layers possible
(or cheap overseas labour)
Photo by Christian Taube, CC-BY-SA 2.5.
Technical Background
Board Technologies
Board Materials
Layer Structure
Most common: FR4
Copper layers
– Epoxy and fibreglass
– Allows traces to cross
– Heat resistant, cheap
– More heat dissipation
High-frequency boards
– More compact board
– Controlled impedance
Surface Layers
– Usable at 1 GHz or more
– Solder mask
– Well-known: Rogers Corp.
– Silkscreen printing
Board Technologies
Components, solder mask, and silkscreen layers on a PCB. Photo by Christian Taube, CC-BY-SA 2.5.
Packages: Through-Hole
Common types of through-hole capacitors
(aluminium × 4, ceramic × 4)
TO (transistor outline): TO-220 (left),
TO-92 (right), metal can, etc.
Axial lead resistor
Diodes in DO-41 package
Inline packages: SIP and DIP (above);
Plastic (PDIP, above), ceramic (CDIP)
Photo credits: Abdullah Al Mamun, CC-BY-SA 2.5 Generic / Wikimedia Commons;
“Nunikasi”, CC-BY-SA 3.0 Unported / Wikimedia Commons; Adafruit Industries, CC-BY-NC-SA, Flickr;
Yves-Laurent Allaert, CC-BY-SA 3.0 Unported / Wikimedia Commons;
Kimmo Palosaari, public domain / Wikimedia Commons;
Packages: Surface Mount (1)
SMD capacitors
Resistors are similar
Sizes in photo:
– 1206, 1206, 0603, 0603
– 1210, 1206, 0805, 0805
– 1812, 1812, 1206, 1210
Photo credits:
“Shaddack”, public domain / Wikimedia Commons.
Packages: Surface Mount (2)
(3-pin small-outline transistor 23)
SO-8 (“SOIC” family)
(with PDIP for comparison)
Left to right: SOIC-14,
SSOP16, QFN-28
QFP40 (40-pin quad flat pack)
0.65mm pitch
BGA-16 (left, top and bottom
of package), with SOT23-6
Photo credits: All images on this slide from Wikimedia Commons.
“Leapfrog”, public domain; “Swift.Hg”, CC-BY-SA3.0 Unported; “SPHL”, CC-BY-SA 3.0 Unported;
“NobbiP”, CC-BY-SA 3.0 Unported; “NobbiP”, CC-BY-SA 3.0 Unported.
Design Software
Eagle (Win)
Cadence OrCAD/Allegro
DipTrace (Win/Mac/Lin)
Altium Designer
KiCad (Win/Mac/Lin)
Agilent ADS
gEDA (Linux)
Mfg’s software
Design Process
Component Selection
Courses vs. real world
– Class: “100nF capacitor”
– Real world: What?!
 Material; polarised?
 Maximum voltage
 Physical size/package
Photo by John Fader. CC-BY-SA 3.0.
 Heat capacity
 Error tolerance
 Cost!!
– Digi-Key: 10HV23B104KN
– 100nF, 1kV, 10%, $70 ea.
Photo by Megger Ltd. CC-BY 3.0.
Component Placement
Balance of objectives
– Room for traces
– Compactness (cost)
– Heat dissipation
– Design simplicity
– Assembly (soldering)
IC pin layouts
– Common sense atypical
– Dictated by IC structure
– Deal with it
Photo by Nicholas Wang (modified). CC-BY-SA 2.0.
Component Pinout Example
From the CD4543BE datasheet (Texas
Instruments). Used for illustrative purposes.
Yes, you are reading the diagram correctly. The
pinout uses order A-D-B-C and A-B-C-D-E-G-F.
Routing Techniques: Traces
Like wires on a PCB
Point A to point B
Angled lines
Can’t cross each other
Usually CNC milled
– Avoid right angles
– Avoid T junctions
Classic PCB “look”
Photo by Creativity103 (flickr). CC-BY 2.0.
Routing Techniques: Vias
Connect layers
– All: Straight through
– Some: Buried/blind vias
 Difficult and expensive
Allows trace “tunnels”
– Pass under another trace
Tips for vias
– Through hole pads = vias!
– Allow for extra space
– High current: more vias
Photo by Karl-Ludwig G. Poggemann. CC-BY 2.0.
Routing Techniques: Copper Pour
Large area of copper
– High thermal capacity
– Large current capacity
– Obstacle for traces
– Obvious light colour
Copper pour tips
– Might need thermals
– Can have vias in them
– Island/deadzone removal
– Software priority order
Photo by t0msk (flickr). CC-BY-NC-SA 2.0.
Practical Strategies
Ground/power planes
Routing components
– Pours cover whole layer
– Take advantage of mask!
– Common in 4+ layer PCB
 Traces between pins
– Lowest priority
– Traces under SMD pads
– Many and/or larger vias
Fabrication constraints
Can use several pours
– DRC limits
– Battery/supply voltage
– Regulated voltage
– Logic level voltage
– Multiple grounds
 Trace-trace clearance
 Board edge clearance
 Trace-pad clearance
– Real-world drill sizes
External Connections
Pin Headers
Dedicated Connectors
– JST/Servo
– Computer Cables
– Barrel Connectors
Chassis Mounting
– Routing / Fabrication
– Gold Fingers
– Tab Routing
– Arduino Shields
Connector Examples
Photo credits (clockwise from top left):
oomlout (flickr), CC-BY-SA 3.0; Appaloosa, CC-BY-SA 3.0 / Wikimedia Commons; M7, public
domain / Wikimedia Commons; Mike1024, public domain / Wikimedia Commons
High-Frequency Considerations
Multilayer Design
Board RF Behavior
Problems Alleviated
– Transmission line effects
– Ground loops
– Digital circuit switching
– Intentional antennas
– Unintentional antennas
Controlled Impedance
– Simulation / fabrication
 Traces to ground have
impedance in real world!
– Crosstalk
Internal Planes
– “Free” capacitor
– Buried/blind vias
Photo by Windell Oskay. CC-BY 2.0.
Design Walkthrough Activity
Design a PCB from start to finish!
Link to PCB software:
Alarm/Buzzer Module
Schematic: Alarm/buzzer module
Alarm/Buzzer Module
How it works:
– When TRIG is LO (0V): nothing happens (low power)
– When TRIG is HI (5V): buzzer sounds (higher power)
– TRIG short circuit to ground same as LOW
– TRIG open circuit same as HI (pull-up resistor)
Ideas for the module
– Plug a switch in between TRIG and GND
– Use reed switch on a door frame and a magnet on door!
– Make a microcontroller module to control the alarm
– Arm/disarm, intruder detection, alarm patterns, etc.
To Do List
Basic schematic capture
– Choose components
– Connect with wires
Custom components
– LM555CN
 Custom symbol (pins)
 Standard DIP8 pattern
– Speaker custom symbol and
Convert to PCB
Routing the board
– Create board outline
– Ground and power planes
– Target size: 5cm × 8cm
– Traces for programming
– Pre-place components
– Check drill sizes
– Verify packages and sizes
– Prepare for manufacturing
Board Layout
Sample PCB layout:
top layer (left) and bottom layer (right)
Ready for Manufacturing
Sample PCB Gerber file (bottom layer traces)
Ready for Manufacturing
How can you manufacture your design?
Do it yourself with traditional methods
– Photosensitive two-sided copper boards
– Regular copper board + a laser printer + glossy paper
– In all cases: ferric chloride to eat away unwanted copper
Get a fab house to do it
– Many companies can do prototypes/small orders for cheap
– APCircuit (Alberta,
– Advanced Circuits (US,
– ITEAD (China,
– SeeedStudio (China,
– OSHPark (US,
Want to learn more?
More details and “good practices” for PCBs?
Want to start getting into advanced PCB design?
– High power and high current design
 Copper thickness (“weight”: standard is 1 oz)
 Maximum current through a trace
 Isolation slots, circuit isolation
– High frequency design (100MHz to many GHz)
 Transmission line effects, microstrip design… (ELEC351/353/453)
 Cross-talk, resonant circuit layout, etc.
Thank you for participating
in this workshop!
Questions? [email protected]
This work is licensed under the Creative Commons BY-NC-SA 3.0 Unported License. To view a copy of this license,
visit or send a letter to Creative Commons, 444 Castro Street,
Suite 900, Mountain View, California, 94041, USA.
Copyright © 2013-2014 the Institute of Electrical and Electronics Engineers, Inc. Contributors: Marc-Alexandre
Chan, Ryan Desgroseilliers.

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