Unit 9 PowerPoint Slides

EET 2261 Unit 9
Read Almy, Chapters 17 – 19.
Homework #9 and Lab #9 due next
Quiz next week.
•An interrupt is a mechanism for causing a
program to temporarily suspend what it’s doing,
and do something else instead.
•Interrupts are commonly used with I/O devices
(keyboards, etc.). By using interrupt-driven
I/O, a program can efficiently service the I/O
devices only when they need attention.
•The alternative is polled I/O, in which the
program periodically stops what it’s doing and
checks to see whether any I/O device needs
An Analogy
•Suppose you’re at home working on a
demanding task (writing a paper), and at the
same time you’re waiting for FedEx to deliver
an important package.
•Two possible approaches:
1. Get up from your desk every 30 seconds
to look out the window for the FedEx
2. Focus on writing your paper, and let the
FedEx driver ring the doorbell to
announce her arrival.
An Analogy (Continued)
•On this analogy:
•Your paper-writing task is like the
processor’s main program.
•The FedEx delivery is like an I/O device.
•The first approach (getting up from your
desk every 30 seconds) is like polled I/O.
Not a good way to work, is it?
•The second approach (relying on the
doorbell) is like interrupt-driven I/O. Makes
better use of your time!
An Analogy (Continued)
•In real life, there may be many different events
that could interrupt you from your primary task:
Tornado siren
Dog scratching at the door to be let out
•Similarly, the HCS12 has many (about 50)
different kinds of interrupts that may require the
CPU to temporarily set aside its main task.
•Some of these interrupts come from outside
the HCS12 chip, and some come from circuits
on the HCS12 chip itself.
List of Interrupts
•For complete list, see pages 75-76 of the
Device User Guide (or the similar list on page
157 of the book).
•The list orders interrupts from highest priority
to lowest. (Priority comes into play if two
interrupts occur at the same time.)
Resets, Traps, and Interrupts
•Of the 50-plus kinds of “interrupts,” the three
highest-priority ones are more correctly called
•Clock Monitor Fail Reset
•Computer Operating Properly (COP) Reset
•The next two highest-priority ones are more
correctly called traps:
•Unimplemented Instruction Trap
•Software Interrupt (SWI) Trap
•The rest are just called interrupts. These are
the ones we’ll focus on.
Allowing or Blocking Interrupts
•The programmer can choose whether to allow
or block interrupts. (But resets and traps cannot
be blocked.) If an interrupt is blocked, it will be
ignored by the CPU.
•We’ll see later that many special function
registers hold bits that let the user allow or
block specific kinds of interrupts.
•Two bits in the Condition Code Register (CCR)
also play a key role in allowing or blocking
Review: Condition Code Register
The CCR is an 8-bit register that contains:
• 5 flag bits (H, N, Z, V, C)
• 2 interrupt mask bits (X and I)
• STOP instruction control bit (S)
CCR Bits X and I
•The X bit blocks (if X=1) or allows (if X=0)
interrupts from the chip’s XIRQ pin. See page
25 of CPU Reference Manual.
•The I bit blocks (if I=1) or allows (if I=0) all
other interrupts, including interrupts from the
chip’s IRQ pin. See pages 25-26 of CPU
Reference Manual.
Interrupt Service Routine
•Assuming that interrupts are allowed, when
the CPU receives an interrupt signal, it sets
aside whatever it is doing and runs code called
an interrupt service routine (ISR) or interrupt
handler for that specific interrupt.
•The programmer must write these ISRs and
place them in memory. An ISR is basically a
subroutine that gets called automatically when
a interrupt occurs.
Interrupt Vector Table
•For each type of interrupt, there is a fixed
location in memory into which the programmer
must load the starting address of the interrupt
service routine (ISR).
•The group of memory locations set aside to
hold the starting addresses of the ISRs is
called the interrupt vector table.
Location of Interrupt Vector Table
locations $FF00
through $FFFF
are reserved for
the interrupt
vector table.
•Figure from page 26 of
Device User Guide.
Information in Table 5-1
•See Table 5-1 on pages 75-76 of the Device User Guide.
•For each type of interrupt, this table tells us:
to a higher
•The locations
in memory
of can
be masked
the programmer
bit instore
the Condition
the CCR.
of the(CCR).
service routine.
Steps in Executing an Interrupt
•When the HCS12 receives an interrupt, it
follows these steps:
•It finishes executing the current instruction.
•It pushes the contents of PC, Y, X, A, B, and
CCR onto the stack, thus saving a snapshot of
exactly what the CPU was doing before it was
•It fetches the address of the appropriate
interrupt service routine (ISR) from the interrupt
vector table and places this address in the
Program Counter (PC).
•Continues on next slide….
Steps in Executing an Interrupt
•…It sets the I bit in CCR high to ensure that no
other interrupt can interrupt the CPU while it’s
serving the current one.
•It fetches and executes instructions belonging
to the interrupt service routine.
•The last instruction of the interrupt service
routine must be an RTI (Return from Interrupt).
•RTI causes the CPU to pull the original PC, Y,
X, A, B, and CCR values from the stack, thus
restoring the CPU to the state it was in before it
serviced the interrupt.
•It then continues to run the code from where it
left off before the interrupt.
Interrupts and Special Function
•Many of the bits in the chip’s special function
registers are devoted to configuring and
controlling interrupts.
•Most of the bits in these registers are either
•enable bits, which we set or reset to
decide whether we’re allowing interrupts
•or flag bits, which the hardware sets to
indicate that an interrupt has occurred. Your
interrupt service routine should reset these
flags to “clear” the interrupt.
Polling Versus Interrupts for Port H
•Your program named Lab07SwitchesToLEDs
sat in a loop, reading the switches and sending
the switch values to the LEDs:
BRA Back
•A better way is to use an interrupt to tell us
when the switch settings have changed, instead
of repeatedly polling the switches.
Port H Interrupts
•Port H has its own interrupt, which can be
caused by any of the bits in Port H:
•Enabled or disabled by the bits in PIEH:
• Flag bits are in PIFH:
Programming an Interrupt
•Programming an interrupt involves several
steps on the programmer’s part:
1. Enable the interrupt (usually by clearing
the I bit in the CCR and setting one or
more local enable bits).
2. Write the interrupt service routine (ISR),
which is much like a subroutine except it
must end with RTI, not RTS.
3. Place the ISR’s starting address in the
appropriate location within the interrupt
vector table.
Example: Programming an
Skeleton of code for using Port H interrupt:
Note that this example enables interrupts on only one of the bits of
Port H. You might instead need to enable interrupts for several of
the Port H bits, or for all of them.
Clearing the Interrupt Flag Bit
•As part of your interrupt service routine (ISR), be
sure to clear the flag bit that caused the interrupt.
Otherwise, when the HCS12 exits your ISR, the
flag bit will still be set and will immediately cause
another interrupt.
•Strangely, to clear an interrupt flag bit you must
write a 1 to it after having read it while it was a 1.
(You don’t write a 0, which is what you might
•Next slide extends the previous example to
include this step.
Previous Example With Additional
Line to Clear the Interrupt Flag
Skeleton of code for using Port H interrupt:
Other External Interrupts
•We’ve been looking at the Port H interrupt.
Ports J and P have similar interrupts.
•These Port H, J, and P interrupts provide one way to
interrupt the HCS12 when an external event occurs.
•The textbook refers to these interrupts as “key
•None of the other I/O ports (A, B, E, K, M, S, T)
can generate interrupts.
•But two of the HCS12’s other pins, named XIRQ
and IRQ, can also generate interrupts. (IRQ
stands for Interrupt Request.)
Review: CCR Bits X and I
•Recall from above that IRQ interrupts, like
almost all other interrupts, are blocked if the
Condition Code Register’s I bit is equal to 1.
•And XIRQ interrupts are blocked if the
Condition Code Register’s X bit is equal to 1.
XIRQ and IRQ Pins Are Active-Low
•The XIRQ and IRQ pins are active-low. They’re
normally held high, and they generate an
interrupt (assuming they’re not masked by the X
or I bits in the CCR) when they are pulled low.
•That’s why the pin
diagram (on page 52 of
the Device User Guide)
calls them  and
, and why our book
calls them *XIRQ and
Pins Are Shared with Port E
•Note also that pin 56 serves double-duty as
both the  pin and as Port E’s bit 0.
•Also, pin 55 serves double-duty as both the
 pin and as Port E’s bit 1.
•So if you want to use
XIRQ and IRQ interrupts,
you can’t also use bits 0
and 1 of Port E for
general-purpose I/O.
Internal Interrupts
•We’ve ben looking at ways in which external
events can interrupt the HCS12.
•As we’ll see in the weeks ahead, many of the
functional blocks within the HCS12 chip itself can
also generate interrupts. This lets these blocks
force the CPU to temporarily suspend execution
of its current program and service their needs.

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