Report

Smart Non-Default Routing for Clock Power Reduction Andrew B. Kahng , Seokhyeong Kang, Hyein Lee DAC’13 Outline • • • • • • Introduction Problem Formulation Algorithm Implementation Flow Experimental Results Conclusions Introduction • non-default routing rules (NDRs) have become an integral element of clock tree synthesis (CTS) methodology as a means of reducing electromigration (EM) violations and delay variations. Introduction Introduction Introduction Introduction Problem Formulation Problem Formulation • RC modeling of wire is given by Equation (2), where le , we and se are the length, width and spacing of edge e, respectively. Problem Formulation Problem Formulation • We use the Elmore delay model [8] to calculate the delay of clock tree. Problem Formulation • For wire slew calculation, we apply the PERI model [10]. The slew at node v, where s is the clock source. Problem Formulation • The skew constraint should be checked for all pairs of source-to sink timing paths with the upper bound Uk. Problem Formulation • For EM constraints, we use a simplified IRMS model derived from Black’s Equation [12]. Algorithm-Iterative LP Algorithm Algorithm Implementation Flow Experimental Results • We use the Synopsys 32/28nm PDK cell library • We synthesize the designs using Synopsys Design Compiler vF-2011.09 • place-and-route with Cadence Encounter DIS v10.1 • We solve the wire sizing problem formulated above using Mathworks MATLAB R2012b Experimental Results Experimental Results Experimental Results Conclusions • In this work, we have assessed the potential for capacitance and power reduction from “smart NDRs” that substitute narrower-width NDRs for selected clock segments while maintaining all skew, slew, insertion delay and EM reliability criteria.