Presentation Part A - High Speed Digital Systems Lab

Report
High Speed Digital Systems Lab
By :
Genady Paikin, Ariel Tsror
Supervisors :
Inna Rivkin, Rolf Hilgendorf
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Agenda
 Introduction
 Learning Process
 Environment
 LabView
 LabView Problems
 JTag/ChipScope
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Agenda
 Hardware
 Implemented Blocks
 Xilinx Synthesis
 Part B Blocks
 System
 Verification Methods
 Full System Integration
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Introduction
 The project is part of the Sub-Nyquist
sampling and reconstruction card.
 Our goal is to implement DSP unit on
FlexRio FPGA cards under NI LabView
environment.
 Includes integration to the full
system.
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Introduction
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High Level Architecture
Xampling
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Introduction
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Sampling stage
 The sampling stage contain two units:
 Xampling sampling card.
 Expand.
Xampling
Analog in
4X62.5 Mhz
digital
A/D
62.5
Mhz
12X20.8 Mhz
digital
Expand
1:3
(250 1:4
decim.)
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Introduction
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CTF module
 Goal : Detects the Support of x(t) and
forwards it to DSP unit.
 Triggered by :
 Initiation.
 SCD interrupt.
 Based on the OMP (Orthogonal
Matching Pursuit) algorithm.
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Introduction
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DSP module
 Goal: Reconstructs the signal from the
samples.
 The unit receives the samples from the
memory (latency fifo), matrix A from the
memory, and signal support from the CTF
unit.
 The support and samples are coordinated
by the latency fifo.
 The unit performs pseudo-inverse of matrix
A (calculates As) using the signal support,
that is received from the CTF.
 Finally the unit multiplies the delayed
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signal with matrix
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Introduction
SCD module
 Goal: Detects a change of the signal
support.
 The unit uses the signal energy to
decide if the CTF needs to recalculate
the signal support.
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Introduction
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Learning Process
 Composed of 2 independent processes :
 Algorithm :
o System main concept.
o Sampling stage (Xampling and Expand).
o CTF module.
o DSP module.
 LabView :
o LabView main concepts.
o FPGA under LabView.
o Integration.
o Implementing basic units.
• Reading matrix from file to memory on FlexRio FPGA
using LabView environment.
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Learning Process
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LabView
 LabView is a System design platform
and development environment for a
visual programming.
 LabView allows simple integration of
several FPGAs together and simple
control of the FPGAs using Host VI
including importing / exporting file to
/ from the system.
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Environment
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LabView
 There are two options of using VHDL
in LabView VIs :
 CLIP node.
 IP integration node.
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Environment
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LabView
CLIP
Node
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Environment
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LabView
CLIP Node
method
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Environment
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LabView
IP Integration
Node
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Environment
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LabView – Host VI
3 FPGAs
Writes to FPGA
(Clip method)
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Environment
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LabView – Target VI
Reads
from
Host VI
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Environment
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LabView Problems
 Does not support array implementation in VHDL.
 Does not support our packages when using VHDL.
 Very long compilation process.
 LabVIEW software tools don't support multi-core or
even multi-thread processes.
 LabVIEW does not allow stage separation (compilation,
elaboration, synthesizing, rout & map) in order to
isolate or at least to save time.
 Lack of debug tools. There is no access to the inner
signals in the FPGA.
 ChipScope/JTag is not supported (see JTag-issues)
 Lack of tutorials that show usage of VHDL in
LabVIEW.
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Environment
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LabView Problems
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Environment
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LabView Problems
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Environment
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LabView Problems
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Environment
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JTag / ChipScope
JTag is not supported under LabView
environment!
 A critical issue because we cannot
debug our design in the real
hardware.
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Environment
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Block Diagram
DSP
Matrix A
(from memory)
Pseudo
Inverse
As+
Signal support
(from CTF)
A1 A2
Signal’s sample
(from memory)
Multiplication
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Hardware
Reconstructed
signal
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Pseudo-Inverse Diagram
R matrix
As
QR Dec
Matrix
Inverse
R_inv
Pinv(As)
Q matrix
Mat Mult
Interface
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Hardware
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Implemented Blocks
QR-Decomposition.
Matrix Multiplier Interface.
This blocks are Xilinx-oriented.
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Hardware
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Xilinx Synthesis
 While we were trying to convert
Altera oriented code to Xilinx one, we
unfortunately discovered that Altera’s
synthesis is much stronger and also
more efficient than the Xilinx one.
Code that includes complicated loops
(implementing muxes) cannot be
synthesized at all.
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Hardware
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Xilinx Synthesis
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Hardware
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Part B Blocks
 Matrix Inverse – upper triangular
matrix inverter.
 Real Time Multiplier.
 SCD (Signal Change Detector).
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Hardware
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Verification Methods
 Small Blocks Verification via Full DSP
Block.
 After a block is changed from Altera to
Xilinx, a full ModelSim simulation is
executed.
 Furthermore, the block is burned on the
FPGA using LabView in order to confirm
LabView compatibility and time
constrains.
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System
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Verification Methods
 We verify that Matrix A is inverted
correctly using Matlab.
5
10
15
20
5
System
10
15
20
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Full System Integration
Full system integration will be
executed during Part B.
 Once we confirm that all the Xilinx
oriented units work well with LabView,
we will replace all the relevant mathscript
blocks with real hardware ones.
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System
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The End
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