FPGA Introduction - Real Time Distributed Systems Lab

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FPGA Introduction
Hao wang and Jyh-Charn (Steve) Liu
What is an FPGA?
• Field Programmable Gate Array
– Configurable Logic blocks (CLB), interconnection
resources, and I/O pads.
How FPGA works?
• CLB consists of two slices, each of which contains
look-up tables (LUT), registers, multiplexers, and
carry logic.
–
–
–
–
LUT implement logic functions
Registers store data
Multiplexers select the desired output
Carry logic enables fast arithmetic function
• Interconnections are routing resources including
channels, switch boxes, clock distribution
networks, etc.
CLB architecture
• Arrangement of slices within the CLB
Slice diagram
Slice diagram
How LUT works
•
•
•
An 2-input LUT configured as follows implements AND gate
Input 1
Input 2
Output
0
0
0
0
1
0
1
0
0
1
1
1
It can be easily reconfigured to implement OR, XOR, NAND, and NOR gates, which
are the basics to build up more complex functions.
Modern FPGAs have 6-input LUTs which can be cascaded to implement complex
digital circuits.
Interconnection architecture
• Switch box topology
Interconnection architecture
• Interconnection patterns
Which takes more
chip area, logic or
interconnects?
Logic: 20% ~ 30%
Interconnect: 70%
~ 80%
How to Reconfigure FPGA
• Logic block functions and interconnections are specified using
Hardware Description Language (HDL).
• The HDL code is synthesized, mapped, placed ,routed and
download onto the chip by vendor-provided tools
Schematic
capture
Gate-level
netlist
BEGIN CIRCUIT=TEST
INPUT SET_A, SET-B,
DATA, CLOCK,
CLEAR_A, CLEAR_B;
OUTPUT Q, N_Q;
WIRE
SET, N_DATA, CLEAR;
GATE G1=NAND (IN1=SET_A,
IN2=SET_B,
OUT1=SET);
GATE G2=NOT (IN1=DATA,
OUT1=N_DATA);
GATE G3=OR
(IN1=CLEAR_A,
IN2=CLEAR_B,
OUT1=CLEAR);
GATE G4=DFF (IN1=SET, IN2=N_DATA,
IN3=CLOCK, IN4=CLEAR,
OUT1=Q, OUT2=N_Q);
END CIRCUIT=TEST;
Mapping
Packing
Place-andRoute
Fully-routed physical
(CLB-level) netlist
Timing analysis
and timing report
Gate-level netlist
for simulation
SDF (timing info)
for simulation
How to Reconfigure FPGA
• Each time a new configuration is downloaded, the FPGA
behaves like a new chip implementing a new function.
• The configuration is lost when powered off, because theyare
stored in SRAM.
– However, the configuration file can be stored in external storage such
as flash card or PROM so that the chip can automatically load it when
powered on
Why use FPGA?
• Compared to CPU, FPGA has the following benefits
– Performance
– Throughput
– Reliability
• Compared to ASIC, FPGA has the following benefits
– Reconfigurability
– Cost
– Time to market
Benefit over CPU: Performance
• FPGA code runs in real time in nanoseconds.
• All the logic blocks inside FPGA can run
concurrently in parallel, since they are real
hardware circuits.
• If fully utilized, FPGA can implement a high
performance many-core system.
Benefit over CPU : Throughput
• FPGA has many high speed I/O pins to
interface with memory, Ethernet, etc. It has
dedicated channels for peripherals, unlike CPU
whose peripherals share a bus.
• FPGA vendors provide many high speed
communication IP cores.
Benefit over CPU : Reliability
• Software programs are usually built upon
several layers of abstractions (driver, OS, etc)
to help schedule tasks and share resources.
They are at risk of incompatibility, resource
contention, deadline violation, etc.
• FPGA circuitry is a hard implementation,
which is deterministic and well predictable.
Benefit over ASIC : Reconfigurability
• ASIC can only do a specific job. If you want an
extra function after an ASIC has been
manufactured, design another one! While for
FPGA, that is nothing but adding a piece of code
and re-compile it.
• Certain bugs are caught after the ASIC has been
manufactured and distributed to customers. A
recall may put the company into bankrupt. While
for FPGA, developers can fix the bug in the HDL
code and distribute the update to customers.
Benefit over ASIC : Cost
• ASIC development is usually non-recurring
engineering. Product fabrication also costs a
lot of money.
• FPGA vendors produce large volume of chips
so that end users do not need to eat the
fabrication cost. Reconfigurability of FPGA
makes it reusable for different projects.
Benefit over ASIC : Time to market
• ASIC needs cost many man-years to design,
test, validate, and fabricate.
• FPGA development boards usually come with
a rich set of peripherals and IP cores which
makes it ideal for rapid prototyping.
• Questions?
Reference
• Introduction to FPGA Technology: Top 5 Benefits.
http://www.ni.com/white-paper/6984/en#toc1
• FPGA introduction, Ovind Harboe
• http://www.fpga4fun.com/FPGAinfo1.html
• http://en.wikipedia.org/wiki/Fieldprogrammable_gate_array#Architecture
• The Design Warrior's Guide to FPGAs
• Virtex-6 FPGA Configurable Logic Block User Guide
• http://www.cse.unsw.edu.au/~cs4211/seminars/va/VirtexArc
hitecture.html
• http://www.1-core.com/library/digital/fpga-logic-cells/
• http://www.ni.com/white-paper/7440/en

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