Mark-Downing - Center for Detectors

Report
Optical AO WFS Detector Developments
at ESO
Mark Downing, Johann Kolb, Norbert Hubin, Javier Reyes, Manfred Meyer
European Southern Observatory ESO (http://www.eso.org)
Martin Fryer, Paul Jorden, Andrew Payne, Andrew Pike, Rob Simpson, Paul Jerram, Jerome
Pratlong
e2v technologies ltd (http://www.e2v.com)
Bart Dierickx, Arnaud Defernez, Benoit Dupont
Caeleste, Antwerp, Belgium (http://www.caeleste.be)
Jorge Romero
University of Málaga (http://www.uma.es)
Philippe Feautrier, Eric Stadler
Institut de Planétologie et d’Astrophysique de Grenoble (http:// http://ipag.osug.fr/)
Jean-Luc Gach, Philippe Balard, Christian Guillaume
Laboratoire d'Astrophysique de Marseille LAM (http://www.lam.oamp.fr)
09 Oct 2013
Downing Optical AO WFS
1
Outline
• L3Vision CCD220 – developed by e2v on behalf of ESO/OPTICON
– Deployment of AONGC Cameras on VLT AO instruments
– Test Result Summary
1. Trades made with Deep Depletion CCD220
2. Improvements of the HV Clock Design
3. SCTE
• Next challenge → LGSD/NGSD
– Large CMOS Visible AO WFS Imager for the ELT to sample the spot
elongation of Laser Guide Stars
– Specifications
– Wavefront Sensor Architecture and Design
– First results
09 Oct 2013
Downing Optical AO WFS
2
e2v L3Vision CCD220
Metal Buttressed
2Φ 10 Mhz Clocks
for fast image to store
transfer rates.
Store slanted
to allow room
for multiple
outputs.
OP 4
Gain
Registers
OP 3
OP 2
Gain
Registers
Image
Area
Gain
Registers
Image
Area
Store
Area
Store
Area
240x120
24□µm
240x120
24□µm
8 L3Vision Gain
Registers/Outputs
Each 15Mpix./s.
OP 8
OP 7
Gain
Registers
OP 1
OP 6
OP 5
e2v CCD220:
 240x240 24 µm pixels
 Split frame transfer CCD
 8 L3Vision EMCCD outputs
 < 0.1 e- RoN at 1,500 fps
 Integral Peltier for cooling to -50ºC
09 Oct 2013
Downing Optical AO WFS
3
Deployment of AONGC WFS Cameras
ERIS
HAWKI
MUSE
SPHERE
09 Oct 2013
Downing Optical AO WFS
4
CCD220 Impressive
(Measured) Test Results
Requirement
Measured
Frame Rate:
Read noise at gain of 300
Image Area Full Well:
Cosmetics:
# of traps, bright/dark defects
Dark Current: 1200fps & -40ºC
100fps & -50ºC
Specification
> 1,500 fps

>1,200 fps
< 0.2 e-

< 1.0 e-
> 160 ke-

> 5,000 e-
0

< 25
< 0.02 e-/pix/frame
 < 0.04 e-/pix/frame
< 0.05 e-/pix/frame
 Key goal specs are met
 Deep Depletion (highly sought after for better red response) is working as good
as the standard silicon devices.
Next Steps:
•
Increase frame rate to 2,500 fps to extend use to E-ELT XAO (Extreme AO).
•
Test shuttered device CCD219 for pulsed laser guide star applications.
09 Oct 2013
Downing Optical AO WFS
5
Trades made with Deep Depletion Device
•
Deep Depletion enabled devices to be built out of thicker silicon (40µm)
for better red response;
– Highly sought after for applications using Natural Guide Stars.
75% improvement
09 Oct 2013
Downing Optical AO WFS
6
Trades made with Deep Depletion Device
•
Deep Depletion enabled devices to be built out of thicker silicon (40µm)
for better red response;
– Highly sought after for applications using Natural Guide Stars.
•
During charge integration if the image area is simply run into inversion for
lowest dark current like the Std Si device then obtain very poor PSF.
•
•
Has an additional “p” well implant for EMCCD
to work.
A minimum bias is required to “punch-through”
(depletion to extend beyond) this “p” well.
Deep Depletion
Std Si
09 Oct 2013
Downing Optical AO WFS
7
Trades made with Deep Depletion Device
•
Deep Depletion enabled devices to be built out of thicker silicon (40µm)
for better red response;
– Highly sought after for applications using Natural Guide Stars.
•
•
During charge integration if the image area is simply run into inversion for
lowest dark current like the Std Si device then obtain very poor PSF.
Solution is to use Tri-Level clocking to obtain the best trade between PSF
and Dark Current.
– Low Level that takes the device into inversion for low dark current.
– High Level just right for good frame transfer and low Clock Induced Charge.
– Very High Level for integrating charge to tune the PSF.
Integration
Image
Area
Clock
09 Oct 2013
Frame Transfer
Downing Optical AO WFS
Very High Level
-0.5V
High Level
-8V
Low Level
8
Adjust Very High Level to Tune PSF
VInteg=-8V
VInteg=-4V
VInteg=0V
VInteg=4V
VInteg=8V
VInteg=12V
PSF FWHM (pixels)
PSF Vs Integration Voltage
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
Min met at > 2V.

Min.
Goal met at > 8V.
Goal
Min.
Goal
-8
-4
0
4
8
12
16
Integration Voltage
09 Oct 2013
Downing Optical AO WFS
9
and trade with CIC and Dark Current
1200fps
100fps
• As expected CIC does not increase with integration voltage.
• Once out of inversion, dark current does not increase further
with integration voltage.
– thanks to “Intrinsic dithering” – uses the fact that after inversion holes
that have migrated into Si/SiO2 I/F have long release time constant.
• Goal Dark Current and PSF specs are met at 8V.
09 Oct 2013
Downing Optical AO WFS

10
Improvement to Design of HV Clock
7
2
3
0,99
D1
RF rectifier
T1
6
4
V_HI set
f
/
~
~
~/
U2
1 , 5, 8
Peak
Detector
S1
switch
GND
OFF
f
6
3
GND
CCD Rphi2HV
100pF
~ 0V
Peak
Detector
V_LO set
2
GND
1, 5, 8
•
U6
/
~
~
~/
C12
Tpixel
7
ON
C13
Cap
100pF
4
Trans
20-50V
Design → LC resonant circuit
– switch, transformer, and capacitor (includes that of the CCD phases);
– tune to resonate at pixel (switch) frequency;
– simple, low power dissipation.
•
First implementation:
– levels stabilized by simply correction for the integrated difference between
peak and reference level.
– Problem is that it does not respond quickly to transients/disturbances.
•
Both measurements and simulations prove that the resonance circuit is
very sensitive to any changes in the load. The load (the CCD) changes
during read out due to changes in clock (inter) capacitances.
09 Oct 2013
Downing Optical AO WFS
11
At Unity Gain: Flat field is very flat
09 Oct 2013
Downing Optical AO WFS
12
However at gain, flat field varies with readout
•
09 Oct 2013
Oscilloscope shows the amplitude of the HV
Clock varies during a frame read out and
variation is proportional to illumination level.
Downing Optical AO WFS
13
Solution is to use full PID controller
in the feedback loop
7
U2
1 , 5, 8
2
3
Peak
Detector
0,99
PID
D1
RF rectifier
T1
6
4
V_HI set
f
/
~
~
~/
switch
S1
C13
Cap
100pF
GND
4
Trans
PID
f
1, 5, 8
•
GND
CCD Rphi2HV
100pF
Peak
Detector
V_LO set
2
7
6
GND
U6
3
/
~
/
~
~
C12
A properly designed PID controller should respond quickest to
disturbances.
09 Oct 2013
Downing Optical AO WFS
14
Original design with step input
102k
VUpperRectI
3.3n
1k
RupperI3
1p
0
RupperI4
1Meg
CupperI
100p
CupperF1100p IC=0
RupperF2
CupperI1
VUpperRect
RupperI1
25.5k
RupperI2
BAS70-04
DUpper
CupperF2
15V
VupperOpAmpOut
TXFM_HV_Clock_Ver2
X1
10k VupperRf n
V4
Rupperrf n
Cupperrf n
1n
U1
4.7
0
RpriFilt
Rpri
AD825_15V
Vi_p
Vo_p
Vi_n
Vo_n
0
Out
R1
CpriFilter
100n
C1
415p
2 AC 1 0 Pulse(1 2 500u 990.09901n 990.09901n 500u 1m)
-15V
24
Cnegsedy
RFET
100n
100pClowerF2 1Meg
100k
Rnegsecdy
ClowerF3 1u
Vf et
102k
BAS70-04
DLower
3.3n IC=0
RlowerF1
VlowerRf n
ZVN4106F
VUpperRect
RupperI1
Inp
Vinput1
Q1
Rlower3
1n
Clower2
X6
4.7
25.5k
RupperI2
10k
ClowerPlus
15
10k
0 AC 1 0 Pulse(-1 5 0 1n 1n 28.166667n 83.333333n)
CupperI
100p
-2 Pulse(-2 -1 750u 990.09901n 990.09901n)
V2
VlowerPlus1
RlowerOpAmpOut
VlowerOpAmpOut
1uAD825_15V
RlowerI
100k
VLowerRect
RlowerI3
100p
ClowerMinus1
15
1p
VlowerMinus
100
15
VlowerI
RlowerIf ilt1
1u
Clowerf ilt1
ClowerI3
0
RlowerI2
BAS70-04
DUpper
ClowerI2
10
8
TXFM_HV_Clock_Ver2
U1
6
0
Vi_p
0
Vo_p
Rpri
V
CpriFilter
00n
R1
4
Vi_n
Vo_n
2
BAS70-04
DLower
3.3n IC=0
0
24
RFET
-2
Cnegsedy
100n
100pClowerF2 1Meg
100k
Rnegsecdy
ClowerF3 1u
Vf et
RlowerF1
VlowerRf n
ZVN4106F
-4
0
Inp
0.2
0.4
0.6
ClowerPlus
15
0.8
Time/mSecs
Vinput1
Q1
09 Oct 2013
R
1n
Clower
200uSecs/div
Downing Optical
AO WFS
VlowerPlus1
4.7
X6
15
100p
15V
-15V
-15V
BAS70-04
DUpper
Optimised design with step input
X2
TXFM_HV_Clock_Ver2
10k
10k
AD825_15V
VupperOpAmpOut
4.7
10k
10n
RsumF
RInv I
RInv F
0
CupperDerF1 RupperDerI
RpriFilt
CupperDerF2
10k
Rpri
Vderiv
1u IC=0
15V
Rupperrf n
10k
AD825_15V
X5
RsumI1
Vi_n
BAS70-04
DUpper
Vo_n
10k
1k
AD825_15VRupperPI
Vprop
RupperPF
U1
10k
RsumF
10k
X4
1Meg
VupperOpAmpOut 4.7
10k
RInv I
300p IC=0
RInv F
Vi_p
Vo_p
Vi_n
Vo_n
0
Rpri
100p IC=0
RsumI3
X5
-15V
100k
Rnegsecdy
100k
24
Cnegsedy
RFET
100n
Vf et
AD825_15V
CupperIntF3
RlowerF1
ClowerF3
1u
Rnegsecdy
RlowerF1
ClowerF3
1u
Vf et
VlowerRf n
ZVN4106F
-15V
Vinput1
Q1
X6
4.7
Vinput1
Q1
0 AC 1 0 Pulse(-1 5 0 1n 1n 28.166667n 83.333333n)
1u IC=0
-15V
300p IC=0
Vinteg
RupperIntI1
1Meg
CupperIntF41p
RupperIntF2
10k
0 AC 1 0 Pulse(-1 5 0 1n 1n 28.166667n 83.333333n)
RsumI3
AD825_15V
CupperIntF3
ClowerMinus1
15
Rlower3
1n
Clower2
ClowerPlus
15
RlowerOpAmpOut
VlowerOpAmpOut
1uAD825_15V
4.7
CupperIntF1
10k
VlowerPlus1
8.2k
X1
AD825_15V
10k
ClowerPlus
15
Inp
-15V
DLower
33p ClowerF2
10k
100p IC=0
33p ClowerF2
10k
Inp
15V
X2
-15V
C1
415p
BAS70-04
24
Cnegsedy
RFET
100n
ZVN4106F
15V
BAS70-04
DLower
Out
R1
CpriFilter
100n
15V
CupperIntF41p
RupperIntF2
AD825_15V
0
RpriFilt
10k
10Meg
RsumI2
C1
415p
TXFM_HV_Clock_Ver2
15V
RupperIntI1
-15V
2 AC 1 0 Pulse(1 2 300u 1u 1u 92u 600u)
Out
R1
X3
CupperIntF1
10Meg
Cupperrf n
1n
X4
AD825_15V
0
Vo_p
100p
-15V
15V
100 VupperRf n
V4
Vi_p
CupperI
CpriFilter
100n
RupperDerF1
15V
U1
VUpperRect
RupperI1
25.5k
RupperI2
300p
5k
102k
VUpperRectI
RlowerI
100k
VLowerRect
RlowerI3
VlowerPlus1
X6 100p
ClowerI3
0
RlowerI2
1u
VlowerMinus
RlowerOpAmpOut
VlowerOpAmpOut
ClowerI2
1uAD825_15V
VlowerRf n
100
15
VlowerI
RlowerIf ilt1
1u
Clowerf ilt1
8.2k
RlowerI
X1
VlowerMinus
Vinteg
Rlower3
1n
Clower2
100k
VLowerRect
RlowerI3
100p
ClowerMinus1
15
15V
10k
-2 Pulse(-2 -1 1.5m 500n 500n)
V2
1u
-2 Pulse(-2 -1 1.5m 500n 500n)
V2
100
RlowerIf ilt1
1u
Clowerf ilt1
ClowerI3
0
RlowerI2
AD825_15V
-15V
ClowerI2
-15V
12
10
8
V
6
4
2
0
-2
0
09
Oct 2013
Time/mSecs
0.2
0.4
0.6
Downing Optical AO WFS
0.8
1
200uSecs/div
16
15
VlowerI
“Proof of the Pudding”
Afterwards
Before
09 Oct 2013
Downing Optical AO WFS

17
SCTE - Long Tail of Residual Charge
Store section
By reverse clocking the
serial register able to get
all charge in a single pixel
60 register
elements
520 gain
elements
Outputs
09 Oct 2013
Downing Optical AO WFS
18
SCTE - Long Tail of Residual Charge
Lower range expanded
•
L3Vision has
long tail of
residual charge
•
Gain x 400
VROL=-5V
09 Oct 2013
Downing Optical AO WFS
SCTE gets worse with
higher gain and signal
thus need to operate at
lowest gain for the
application.
To keep gain low, need
to optimize for low read
out noise at unity gain.
19
The need for good SCTE
•
•
With Shack Hartmann WFS, if SCTE does not vary much with signal
then it is simply an offset in the centroid that can be subtracted.
However, with pyramid WFS, SCTE appears as cross-talk into
neighboring sub-apertures → spec. is < 1%.
Sub-aperture
09 Oct 2013
Downing Optical AO WFS
20
Gain 400; SCTE Vs Serial Clock Low Level
Amp 0Amp
Best
Amp
5
Least
Best
Amp
• SCTE < 1% is only met when
VROL = -7V; i.e. when serial
register is clocked into inversion.
• Fortunately, Clock Induced
Charge does not increase
significantly.
• Tells us something about where
the charge is being trapped – SiSiO2 I/F
Strategy Followed:
• Set up output amplifier biasing
and serial register to maximize
CIC and dark current as this
guarantees that all charge is
being detected.
VROL=-4V
VROL=-5V
VROL=-6V
VROL=-7V
09 Oct 2013
Downing Optical AO WFS
21
Gain 400: SCTE < 1% for all amplifiers with VROL=-7V
09 Oct 2013
Amp 0
Amp 4
Amp 1
Amp 5
Amp 2
Amp 6
Amp 3
Amp 7
Downing Optical AO WFS

22
Outline
• L3Vision CCD220 – developed by e2v on behalf of ESO/OPTICON
– Deployment of AONGC Cameras on VLT AO instruments
– Test Result Summary
1. Trades made with Deep Depletion CCD220
2. Improvements of the HV Clock Design
3. SCTE
• Next challenge → LGSD/NGSD
– Large CMOS Visible AO WFS for the ELT to sample the spot
elongation of Laser Guide Stars
– Specifications
– Wavefront Sensor Architecture and Design
– First results
09 Oct 2013
Downing Optical AO WFS
23
Block Diagram of Full Size Device; LGSD
44 LVDS Serial Links
Highly integrated
– All analog processing on-chip:
Multiplexer/serializer
Control
Logic
20 x1760 single slope
ADCs
Control
Logic
Pre-amp & Gain of x1/2/4/8
84x84 Sub-apertures
each 20x20 pixels
Y-addressing
Y-addressing
1760x1680
pixels
Pre-Amp & Gain of x1/2/4/8
Control
Logic
20x1760 single slope
ADCs
Multiplexer/serializer
Control
Logic
•
•
•
•
correlated double sampling (CDS),
programmable gain of x1/2/4/8 on the fly,
9/10 bit single slope ADCs,
total effective 12 bit data conversion
– 20 top + 20 bottom rows processed in
parallel to slow the read out per pixel
(34µs) and beat down the noise.
– Fast LVDS serial interface to outside world
• simple digital interface;
• power consumption similar to high speed
drivers to transport analog signals off-chip;
• better guarantee of achieving and
maintaining low noise performance.
Natural Guide Star Detector (NGSD)
pioneering scaled down demonstrator
~ ¼ of full size → non-stitched
44 LVDS Serial Links
09 Oct 2013
Downing Optical AO WFS
24
Specifications of the LGSD (NGSD)
Physical characteristics
Pixel array
(Refn pixels - 40 columns)
1760x1680 (880x840 pixels in NGSD)
- 5x6cm requiring stitched design (>> max. reticle 25.5x32.5mm)
Technology
Thinned backside illuminated CMOS 0.18µm
– TowerJazz APD3; 6 metal layers
Silicon
High resistivity 1000 ohm-cm → targeting thickness of 12µm
Pixel pitch
24µm
Pixel topology
4T pinned photodiode pixel with low noise threshold transistors;
slit wafer run more speculative ultra low threshold → 1e- goal
Array architecture
84x84 time coherent “sub arrays” of 20x20 (8x8 NGSD) pixels
- LGSD image area size of 4x4cm
Shutter
Rolling shutter in chunks of 20 rows
→ synchronous temporal detection within a sub-aperture.
09 Oct 2013
Downing Optical AO WFS
25
Specifications of the LGSD (NGSD)
Read out
Number of rows read in
40 (20 in NGSD) rows in parallel
parallel
Number of ADC’s
40x1760 (20x880 in NGSD) at 9/10 bits
Number of parallel
LVDS channels
88 (22 in NGSD)
Serial LVDS channel bit
210 Mb/s baseline, up to 420 Mb/s (desired)
rate
Frame rate
700 fps up to 1000 fps with degraded performance
2 to 3 Gpixel/s = 20 to 30 Gb/s over 88 parallel LVDS channels
Power dissipation
< 5W , (NGSD 0.5W) including the 88 LVDS drivers
Actual LVDS driver
dissipation per channel
6.0mW at maximum data rate; 4.5 mW in sub-LVDS
09 Oct 2013
Downing Optical AO WFS
26
Specifications of the LGSD/NGSD
Performance
Pixel full well QFW
> 4000 e-
Linearity to full well
< 5%
Read noise including ADC < 3.0 e-RMS
Already
verified in
Technology
Demonstrator
Image lag
<2%
Dark Current
< 0.5 e-/pixel/frame
QE
> 90% at 589nm; optimized for the red
→ BackSide Illumination (BSI)
Point Spread Function
< 0.8 pixel FWHM
Cosmetics
< 0.1% bad pixels
09 Oct 2013
Downing Optical AO WFS
27
Video Chain – single slope ADC
VRST
Column
bus
reset
4T
pixel
VSF
Gray Code
9/10
1
2
Pre-Amp
3
+
-
4
Comparator
x1
x2
Q
D
Q
Parallel
to Serial
x4
Clk
Clk
x8
Copy
p-Si
Ramp
PPD
110MHz
DDR
+
-
n+
D
Sync
B
A
select
transfer
p+
Double
Register
LVDS Out
SN
reset
transfer
signal
• Single slope ADC chosen for
robustness, excellent low noise
and linearity (DNL).
• Good compromise between
speed, precision, power
consumption, and area occupied
09 Oct 2013
video
reset
Latch
code
ramp
offset
comparator
output
Gray code
Downing Optical AO WFS
0
512
28
22x42
subapertures
22x42
subapertures
22x42
subapertures
22x42
subapertures
22x42
subapertures
8800
column
ADCs
&
11 LVDS
8800
column
ADCs
&
11 LVDS
8800
column
ADCs
&
11 LVDS
Corner
22x42
subapertures
20.16mm
Yaddressing
11 LVDS
&
8800
column
ADCs
22x42
subapertures
20.16mm
Yaddressing
Corner
Yaddressing
Corner
09 Oct 2013
11 LVDS
&
8800
column
ADCs
Corner
Corner
Reticle View
11 LVDS
&
8800
column
ADCs
Yaddressing
Corner
8800
column
ADCs
&
11 LVDS
10.08mm
10.56mm
11 LVDS
&
8800
column
ADCs
22x42
subapertures
8800
column
ADCs
&
11 LVDS
22x42
subapertures
11 LVDS
&
8800
column
ADCs
10.56mm
Yaddressing
Yaddressing
20.16mm
10.56mm
10.56mm
Corner
5.28mm
10.56mm
Corner
LGSD Tentative Stitching Plan
Downing Optical AO WFS
29
22x42
subapertures
22x42
subapertures
22x42
subapertures
22x42
subapertures
22x42
subapertures
8800
column
ADCs
&
11 LVDS
8800
column
ADCs
&
11 LVDS
8800
column
ADCs
&
11 LVDS
Corner
22x42
subapertures
20.16mm
Yaddressing
11 LVDS
&
8800
column
ADCs
22x42
subapertures
20.16mm
Yaddressing
Corner
Yaddressing
Corner
09 Oct 2013
11 LVDS
&
8800
column
ADCs
Corner
Corner
Reticle View
11 LVDS
&
8800
column
ADCs
Yaddressing
Corner
8800
column
ADCs
&
11 LVDS
10.08mm
10.56mm
11 LVDS
&
8800
column
ADCs
22x42
subapertures
8800
column
ADCs
&
11 LVDS
22x42
subapertures
11 LVDS
&
8800
column
ADCs
10.56mm
Yaddressing
Yaddressing
20.16mm
10.56mm
10.56mm
Corner
5.28mm
10.56mm
Corner
NGSD anticipates scaling to LGSD
Downing Optical AO WFS
30
Read out
88x42 Sub-Apertures
North Half-Array
20 sets of row select
lines per SA
ADC Gray
Code BUS
4T 24um
pixel
reset, select & transfer
20 lines per
column of
pixel
Subaperture
row
addresses
(1 of 42)
20 rows of column bias & pre-amp with gain
of x1/2/4/8 settable SA by SA
Gain
ADC
Ramp
20x20 pixels
per SA
Random address Control
88x42 Sub-Apertures
South Half-Array
Random address Control
Subaperture
row
addresses
(1 of 42)
Center line
Timing,
clocks and
biases
20 rows of comparators (35,200)
D
Copy
20 rows of Registers A
20 rows of Registers B
Q
D
Q
LRC40 Checksum Calculator
110MHz Clock
DDR
Parallel to serial
LVDS Outputs
Sync
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Downing Optical AO WFS
31
Summary
CCD220:
• Both Std Si and Deep Depletion variants of the CCD220 are
working extremely well, production run of cameras is nearing
completion, and our instrument project managers are now very
happy.
LGSD/NGSD:
• ESO has formed a good partnership with e2v and Caeleste.
• The design of the NGSD is complete and in fabrication.
• Extensive simulations have confirmed correct operation and
performance.
• Devices will be available in the coming months for testing
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32
Thank You
This work has been "partially funded by the OPTICON-JRA2
project of the European Commission FP6 and FP7 program,
under Grant Agreement number 226604"
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33
TVP – optimises pixel deisgn
VRST
reset
Optimize the pixel design to find best trade
between image lag, linearity, gain, and noise
(white and 1/f) by testing:
• pixel variants with different transfer gate
and transistor geometries;
• different threshold voltages of the nmos
transistors;
• extra implants to improve image lag.
VSF
1
select
2
3
transfer
4
n+
p+
p-Si
Column
bus
Pinned photodiode
p+ implant
p implant
transfer gate
reset
select
09 Oct 2013
Downing Optical AO WFS
34

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