Interrupt

Report
Introduction to Interrupts
Outline of the lecture:
Chandana:
1. Introduction
2. Example
3. Definition
4. Vector table and Maskable/nonmaskable interrupts
________________________________________________
Hao:
5. Stack status
6. HPRIO
7. Example
1
Polling and Interrupts
• Polling- Imagine a
phone without a bell.
You would have to
periodically answer
the phone to see if
anyone is there
• Interrupt – Phone
with a bell. You can
do something else
and stop and
answer the phone
when it rings
2
Polling Pros and Cons
Pros
• Simple
Implementation
• Good for single I/O
cases
• Doesn’t need extra
hardware
Cons
• Inefficient for
complex systems
• May not be fast
enough for
requirements
3
Interrupts Pros vs. Cons
Pros
• Efficient for complex
systems (great
multitasking)
• Can be ignored
(masked)
• Can be prioritized
Cons
• Tradeoff of
hardware complexity
• Can make
debugging difficult
due to unanticipated
random occurrences
4
Applications
•
•
•
•
Computer Keyboard
Stability Control System on Car
House security system
Pause button on television
5
Ways Interrupts can be generated
Hardware Interrupts
Software Interrupts
• Peripherals such as
a printer or fax
machine
• Computer Operator
via keyboard, mouse
or power on reset
button
• Another computer
•
•
•
•
Timer resets
Timer interrupts
Traps
Request for input or
output
• Arithmetic overflow
error
6
Some Definitions
•
Interrupt Service Routine
(interrupt handler): This is a
“more important” instruction code
that interrupts your main program
code. The routine is specific to the
type of interrupt called.
•
Interrupt Vector: This is an
address in memory where the ISR
instruction code is located. It is the
starting address of the code. (Like a
pointer)
•
$FFF6
Interrupt Vector Table: This is a
table indicating the interrupt vector
7
Interrupt Flow
Interrupt condition
is met
YES
A
B
Analyze Priority
ISR instruction
Mask(s) set?
Set (I) or (X)
to prohibit another
Interrupt
NO
Complete Current
Instruction
Store all registers
on the Stack
Continue
Program
A
Standard Interrupt
Table
Load Address in
appropriate vector
B
RTI
NO
YES
Clear I or X bit in
CCR
Restore Registers
w/ org. Values
Non-Maskable Interrupts
• 6 Non-Maskable
Interrupts
1. POR of RESET pin
2. Clock monitor reset
3. COP watchdog
reset
4. Unimplemented
instruction trap
5. Software interrupt
(SWI)
6. XIRQ interrupt
• Higher Priority than
maskable interrupts
• Can interrupt Maskable
Interrupt ISRs
• X=1 ONLY disables
XIRQ interrupt (and all
other interrupts are still
enabled when X=1)
9
XIRQ & IRQ
10
Non-Maskable Interrupts
•
At Reset or during Non-Maskable interrupt
–
–
•
Clear X bit
–
–
•
•
X=1 and I=1
Interrupts cannot be serviced
TAP instruction
ANDCC #$40 instruction
Software cannot set X bit once cleared unless non-maskable interrupt
occurs
RTI restores X and I bits to pre-interrupt state
Non-Maskable Interrupts
• XIRQ
– Externally triggered
– PE0 pin low = XIRQ interrupt
• SWI
– Allows an interrupt without an event
– MON12 in use: jumps back to DBug12
• Unimplemented Instruction Trap
– CPU is given code with invalid opcode
– Generates interrupt request to unimplemented
instruction trap vector
12
Maskable Interrupts
•
27 Maskable Interrupts
– Global Masking: controls
execution of all maskable
interrupts (ie. I bit =1, no
maskable interrupts occur)
– Local Masking: controls
execution of interrupt on a
peripheral device (ie. ATD)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
13
IRQ
Real-Time Interrupt
Standard Timer Channel 0
Standard Timer Channel 1
Standard Timer Channel 2
Standard Timer Channel 3
Standard Timer Channel 4
Standard Timer Channel 5
Standard Timer Channel 6
Standard Timer Channel 7
Standard Timer Overflow
Pulse Accumulator A Overflow
Pulse Accumulator Input Edge
SPI transfer Complete
SCI system
ATD
Port J
CRG PLL Lock
CRG Self Clock Mode
Flash
CAN Wakeup
CAN Errors
CAN Receive
CAN Transmit
Port P
PWM Emergency Shutdown
VREG LVI
Maskable Interrupts
• IRQ
• Only external maskable interrupt signal
• IRQE bit on IRQCR Register
• IRQE=1: High level-Sensitive
• IRQE=0: Low Level-Sensitive
• Peripheral Subsystems (all other Maskable
Interrupts)
• Flag bit and interrupt enable bit
• ATD, Timers, PWM, serial communications,
etc.
14
Interrupt Vector Tables
15
Interrupt Vector in Mon12
MON12 interrupt vectors are used. ($0F00-$0FFF )
MON12’s calls ISR’s
specified by the user in
the $0Fxx range
The microcontroller
calls ISR’s specified
in the $FFxx range.
16
Interrupts: Stack
Higher Address
Stack Pointer
before Interrupt
RTN LO
First Pushed In
Last Pulled Off
RTN HI
Y LO
Y HI
X LO
X HI
Last Pushed In
ACC A
First Pulled Off
ACC B
CCR
Lower Address
•
•
•
•
•
RTN – address of next instruction in Main
Program, upon return from interrupt.
X LO and Y LO are the low bytes of X and Y
registers.
X HI and Y HI are the high bytes of X and Y
registers.
ACC A and ACC B are the accumulators.
CCR is the Code Condition Register
Stack Pointer
after Interrupt
Highest Priority Interrupt (HPRIO) Register
Address: $001F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
1
1
0
1
1
1
1
PSEL7
PSEL6
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
Bit 0
-
• HPRIO register moves one maskable interrupt
to top of priority list
• Cannot change priority of non-maskable
interrupts
• Procedures to increase priority of maskable
interrupt:
– Set I bit to disable maskable interrupts
– Write low byte of the starting interrupt vector address to HPRIO
– Clear I bit to re-enable maskable interrupts
Highest Priority Interrupt Register (HPRIO)
Address: $001F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
0
1
1
1
1
0
PSEL7
PSEL6
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
-
• PSEL[7:1] – Priority Select Bits
– Write the low byte of the starting maskable interrupt vector to
HPRIO to elevate that maskable interrupt to the highest priority
– Ex: writing $DE (#%11011110) to HPRIO elevates the Standard
Timer Overflow to highest priority (Standard Timer Overflow
vector = $FFDE & $FFDF)
ATD Interrupt Example : ISR
• Polling code from our Lab 2:
CHECK LDX #ATDSTAT0
BRCLR $00,X #%1000000 CHECK * Wait until conversion completes
• Write an Interrupt Service Routine (ISR) to be
run to print out the ATD results when
conversion is finished
• Other programs still running during the
conversion
• Continuous conversion
ATD Interrupt Example : ISR
*Interrupt Service Routine
ORG
LDAA
STAA
$2000
ATDDR0H
LSTCONV
LDAA
#$00
LDAB
LSTCONV
LDX
#51
IDIV
XGDX
ADDB
#$30
STAB
V1
XGDX
LDAA
#10
MUL
LDX
#51
IDIV
XGDX
ADDB
#$30
STAB
V2
LDX #STRING1
JSR OUTSTRG
LDAA
STAA
RTI
Define a starting address
Read ATD result register
Store value to a reserved memory location
*Load D with LSTCONV
*Load x with #51
*Divides D by X ->D:X
*Stores B to v1
*Load A with 10
*Multiply A and B (low byte of D)
Convert value and print to screen
*Stores B to v2
#%00010000 *Scan=0, MULT=0, CC:CA=000 (AN0)
ATDCTL5
*Start Conversion by setting ATDCTL5
Writing to ATDCTL5, only convert data from AN0
Ensures that we will get the next interrupt (SCF is cleared)
Finally, call RTI to return from the ISR and pull
CPU register values back from the stack
ATD Interrupt Example: Setup
• Set up interrupt vector table for the ATD
Interrupt
– Write the address of the first instruction of the ISR
($2000) to ATD interrupt vector ($0FD2)
• Enable ATD interrupt
– Setting ASCIE bit (ATDCTL2) to enable ATD
interrupts (local mask)
• Enable global maskable interrupts
• Processor is then free to run other code
ATD Interrupt Example: Setup
ORG
SEI
LDX
STX
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDY
L1 DEY
BNE
CLI
LDAA
STAA
$1000
Set I bit to make Interrupt Vector Table changes safe
#$2000
$0FD2
#%10000010
ATDCTL2
#%00001000
ATDCTL3
#%10000101
ATDCTL4
#100
L1
Store the address of our ISR ($2000) to the Interrupt Vector for the ATD ($0FD2)
Set the ASCIE bit (bit 1 in ATDCTL2) to enable local ATD interrupts
Set that only one conversion each sequence
Set ATD resolution and prescale
Wait for the ATD to fully power up
Clear the I-bit to enable all maskable interrupts
#%00000000
ATDCTL5
Starting conversion by setting ATDCTL5, Scan=0, MULT=0, CC:CA=000 (AN0)
ATD Interrupt Example: Full Code
ATDCTL2
ATDCTL3
ATDCTL4
ATDCTL5
ATDSTAT0
ATDDR0H
EQU
EQU
EQU
EQU
EQU
EQU
$0082
$0083
$0084
$0085
$0086
$0090
LSTCONV
OUTSTRG
EQU
EQU
$800
$FF5E
ORG
STRING1
V1
RMB
FCC
V2
RMB
FCC
FCB
$802
FCC
1
"."
1
" Volts"
$0A,$0D,$04
ORG
SEI
LDX
STX
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDY
L1
DEY
BNE
CLI
LDAA
STAA
ATDCTL5
$1000
#$2000
$0FD2
#%10000010
ATDCTL2
#%00001000
ATDCTL3
#%10000101
ATDCTL4
#100
*Interrupt Service Routine
Define Constants
(ex: ATDCTL4)
"The voltage is "
Define Strings and
reserve memory
Setup ADC and
ADC Interrupt
*Start address of ISR
*ATD Service Routine Vector
*ADPU = 1, ASCIE=1, ASCIF=0
* one conversion each sequence
*Resolution and prescale
*ATD Converter Startup Delay
*Scan=0, MULT=0, CC:CA=000 (AN0)
*Start Conversion by setting
…………
*All kinds of programs
Loop
*******
*Many other calculations may be performed here
******
JMP Loop
SWI
END
$2000
ATDDR0H
LSTCONV
LDAA
LDAB
LDX
IDIV
XGDX
ADDB
STAB
XGDX
LDAA
MUL
LDX
IDIV
XGDX
ADDB
STAB
LDX #STRING1
JSR OUTSTRG
#$00
LSTCONV
#51
LDAA
STAA
#%00010000
ATDCTL5
RTI
L1
#%00000000
ATDCTL5
ORG
LDAA
STAA
Run any other code
#$30
V1
#10
#51
Interrupt Service Routine
*Load D with LSTCONV
*Load x with #51
*Divides D by X ->D:X
*Stores B to v1
*Load A with 10
*Multiply A and B (low byte of D)
Convert value and print to screen
#$30
V2
*Stores B to v2
Start next conversion
*Scan=0, MULT=0, CC:CA=000 (AN0)
*Start Conversion by setting ATDCTL5
Back to main program

similar documents