### IP Power Model generation

```Power modeling flow for a power
analysis at system level
Cyril Chevalier, Audrey Le-Clercq, Diana Moisuc
STMicroelectronics
Philippe Garrault
Docea Power
Content



Power modeling at system level: need, usage and
requirement
IP power characterization
IP power modeling: HW power model, Use case power
model

Hierarchical power modeling

Use case power modeling

Some system level results
ESL power analysis general purposes
Use cases
modeling
Thermal
model
Trace from SW
simulation
or board validation
Power
model
Power aware
SW simulation
Architectural
performance
model
TLM/SystC
virtual
platform
Aceplorer
 POWER ARCHITECTURE EXPLORATION
 POWER BUDGET TRACKING
 THERMAL ANALYSIS
 POWER MANAGEMENT SW
HELP
TO
DECISION
SW
Panic chez l’architect
Marketing to Customer:
Marketing to System Architects:
Sure, our
devices are
very
competitive
with
regards to
power!
I need to model the power behaviour
of the whole SoC/chipset. I need to
model all the use cases!!
How do I get the data?
Can I trust the data I am getting?
Can I trust my model?
System design flow
Early
architecture
Architecture
validation
Power aware SW
development
Performances architecture model
PM SW
debug
SystC-TLM platform
Power architecture model
UC Power Tracking
Thermal model
Dynamic thermal management simulation
PM SW
debug
System modeling for accuracy : a bottom-up flow
Use case
analysis
Performance
analysis
System architecture
Use case description
Power estimation
Sw constraints
AMS architecture
Power model
Power model
3rd party IP
IP estimation
RF architecture
Soc architecture
Power model
for estimation
Power model
Power model
Sub-system 1
Power model
Power model
Sub-system 2
Sub-system 3
IP estimation
IP estimation
IP estimation
power
IP
IP power
estimatio
estimation
n
IP Power characterization for power modeling

Power(Power Statei) = f(Param1, Param2,....)
• Parameters: voltage, clock frequency, activity, process
and temperature

IP Characterization process:
 Power states & parameters identification
Architect
Designer
 Characterization: Simulations, Measures
 Conditions & Power figures reporting in a Power Card
Designer
 Power model library
Example: Audio Sub-System
5 power states
 5 power states:
•
•
•
•
•
Idle,
Always On,
Music Playback,
CS Call,
Max Activity
Parameters
 2 Power supplies:
• Vlogic,
• Vmem

3 clocks
P(CS Call) = f(Vlogic, Vmem, Clock1, Clock2, Clock3)
IP power characterization flow
Power figures collection : IP
Param_1
Flow inputs levels
Specification targets, IP description
…
Power card
Param_n
Dynamic
Power
PS1
Activity
file
per
power
state : PSi
IP design flow
PS2
RTL Pwr Estimate
…
PSn
Power states
Dynamic pwr
Per pwr state
Gate Pwr Estimate
V
Leak
PS1
IP level: Simulation environment
PS2
Pwr Measures
PSn
Validation environment
…
Leakage per
power state
IP Power Model generation
IP Power card
V
Ck
Func
param
IP Power Model
Dyn
Power
PS1
Aceplorer
PS2
…
PSn
V
Leak
Power model
generation
Power model
update
PS1
PS2
Parameters
Parameters
default
Parameterized
values
default
values
Parameters
Equations of
Dynamic and
Leakage Power
consumption
…
PSn
Each IP must have
its Power Card
current
equations
IP power model library
IP Power
Model
IP Power
Model
IP Power
IP
Power
Model
Modeli
IP power use case model
IP power states
IP power model
PS1
Scenario
Pwr(PS1)
t1
Pwr(PS2)
Pwr(PS3)
Pwr (W)
PS4
PS2
t2
t3
PS1
t4
Pwr(PS4)
Pwr(PS5)
Pwr(
PS4)
Pwr(PS6)
Pwr(PS7)
Pwr(PS1)
t2
t1
IP power model library
IP UC Power
Modeli
IP Power
IP Power
Model
i
Model
i
IP Power
Modeli
Pwr(
PS2)
t3
Pwr(
PS1)
t4
Hierarchical model & scenario creation
Vdd2
IP power model library
•
•
Top
Power model
UC model
instantiation
Vdd1
C1
Modeling
Interface
Aceplorer
MC1
MC2
C2
C3
MC3
Hierarchy
capture
Scenario
description
time
TL-PS1
MC1
C2
TL-PS4
MC1-PS1
C3-PS4
TL-PS2
TL-PS1
MC1-PS2
C3-PS2
C3-PS1
Aceplorer
Conclusion
Power modeling flow

Formal modeling flow : model standardization
• Data traceability
• Easier model debug
• High readability : communication tool bw many users

Fast system power model development

Upgradeable models for accuracy as needed
Next work


use cases power trace usage
Use cases development for power model correlation with on board
validation
```