Report

A 3D IC Designs Partitioning Algorithm with Power Consideration Ho-Lin Chang, Hsiang-Cheng Lai, Tsu-Yun Hsueh, Wei-Kai Cheng, Mely Chen Chi Department of Information and Computer Engineering, CYCU ISQED’12 Outline • • • • • Introduction Problem Description Power Estimation Partition Algorithm Experiment Results 2 Introduction • 3D stacking technology is likely to become a popular trend in 3D IC designs. It has several advantages [2-6]. – higher integration density – higher performance – Lower power consumption • In order to supply power to every layer from the power/ground pads, which are located on the bottom layer, power TSVs are needed. – A power TSV is a TSV used only for transporting power. – There is a maximum power allowed for one power TSV. • The total number of power TSVs in the circuit will be less if the higher layers consume less power than the lower layers. 3 Problem Description • Input – – – – – – – Gate level netlist Number of layers of the 3D IC(k) Operating frequency of each primary input Supply voltages Standard cell library TSV cells Power density constraints of some layer of 3D IC • Objective – Partition the netlist into k layer to minimize the total number of TSVs( Signal and power TSVs) and area overhead under the designed power density constraints. 4 Problem Description • AreaOverhead AreaOverhead = (( x K ) – Aorigional ) / Aorigional – Where is the maximum area of layer among all layers, – Aorigional is the total Area of origional 2D design that dosen’t containt TSV’s. • Power density Power_density = • Face to back stacking style • I/O Pads are all located at the first layer 5 Power Estimation 6 Power Estimation The average power model consists of the following factors: 1. the total power of the input pins of the standard cells, 2. the total capacitive loading of the output pins of the standard cells, 3. the total power consumption of the I/O pads, 4. the total power of storage elements (e.g. D-type flip-flops) for data retention, 5. the operating frequency and the supply voltage of all the cells. It can be calculated with the following equation: PowerAVG = Powercore +PowerPAD 7 Power Estimation • The current core I for the core and the current PAD I for the pads are • The total number of power/ground pads required by core and I/O pads are (The area of these pads will be added on the first layer ) Where Ilimit_pad is the maximum current allowed of a P/G pad. • The number of power TSVs required by the layer i is Where Ilimit_TSV is the maximum current allowed of a power TSV. 8 Partition Algorithm 1. 2. 3. 4. 5. Coarsening Initial Partitioning 3D-Aware k-layer-Partitioning and uncoarsening Layer Swapping Area Overhead Refinement 9 Partition Algorithm • Coarsening – Visit a net and choose the least pin number cell of the net. – Made pair with everyone other cells in the net • Build EIA Table (External net , Internal net , Area ) by each pair For net 5, choose C4 and make pair (C4,C6) E = 2, I =2, Area = Area(C4) + Area(C6) – – – – Visit another net until all nets have been visited. Sort the EIA Table by less external nets, more internal nets, and smaller area. Coarsen the pair in the EIA Table sequentially. Multilevel coarsening. 10 Partition Algorithm • Initial Partitioning – Place all module on the first layer – Successively Move the module with maximum gain to the next upper layer until Afirst layer ≤ Aavg – Apply an area constraint FM algorithm. 11 Partition Algorithm • 3D-Aware k-layer-Partitioning and uncoarsening gain = size of old cut set – size of new cut set – (1) simultaneous k-way partition – (2) successive two-way partition for k layers with Power density constraints. • Record each state satisfied Power density constraint • The state with least partial sum will be chosen as the result of the partition 12 Partition Algorithm • Layer Swapping – k! permutations among all layer – Calculate the power TSVs and signal TSVs among all layer permutations – Record the result of the minimum total TSVs 13 Partition Algorithm • Area Overhead Refinement – Move cells of zero gain with the largest layer area to smaller area layer – Update area comparison during each cell move – Stop when no more zero gain cells in the largest area layer 14 Experiment Results 15 Experiment Results 16 Ex_hMetis is provide by [6] Experiment Results 17 Experiment Results 18 Experiment Results 19 Conclusions • This paper present an efficient algorithm to partition a circuit into k layers under power density constraints. • Use multilevel structure and successive 2-way partition to minimize number of TSVs and area overhead. • This result are better than all teams in the IC/CAD 2011 contest in Taiwan. • The successive 2-way partition method is superior tho the extened hMetis method in terms of both the number of TSVs and run Time. 20