Emerging Research Logic Devices1 PIDS ITWG Emerging New

Report
ITRS Public Conference
Emerging Research Devices
2011 ERD Chapter
Jim Hutchby – SRC
July 13, 2011
1 ERD
2011 ITRS Summer Conference – San Francisco – July 13, 2011
Emerging Research Devices Working Group


































Hiroyugi Akinaga
Tetsuya Asai
Yuji Awano
George Bourianoff
Michel Brillouet
Joe Brewer
John Carruthers
Ralph Cavin
An Chen
U-In Chung
Byung Jin Cho
Sung Woong Chung
Luigi Colombo
Shamik Das
Erik DeBenedictis
Simon Deleonibus
Bob Fontana
Paul Franzon
Akira Fujiwara
Christian Gamrat
Mike Garner
Dan Hammerstrom
Wilfried Haensch
Tsuyoshi Hasegawa
Shigenori Hayashi
Dan Herr
Toshiro Hiramoto
Matsuo Hidaka
Jim Hutchby
Adrian Ionescu
Kiyoshi Kawabata
Seiichiro Kawamura
Suhwan Kim
Hyoungjoon Kim
2 ERD WG 12/05/10 & 12/2/10
AIST
Hokkaido U.
Keio U.
Intel
CEA/LETI
U. Florida
PSU
SRC
GLFOUNDRIES
Samsung
KAIST
Hynix
TI
Mitre
SNL
LETI
IBM
NCSU
NTT
CEA
Intel
PSU
IBM
NIMS
Matsushita
SRC
U. Tokyo
ISTEK
SRC
EPFL
Renesas Tech
Selete
Seoul Nation U
Samsung
 Atsuhiro Kinoshita
 Dae-Hong Ko
 Hiroshi Kotaki
 Mark Kryder
 Zoran Krivokapic
 Kee-Won Kwon
Jong-Ho Lee
 Lou Lome
 Hiroshi Mizuta
 Matt Marinella
 Kwok Ng
 Fumiyuki Nihei
 Ferdinand Peper
 Yaw Obeng
 Dave Roberts
 Barry Schechtman
 Sadas Shankar
 Atsushi Shiota
 Satoshi Sugahara
 Shin-ichi Takagi
 Ken Uchida
 Thomas Vogelsang
 Yasuo Wada
 Rainer Waser
 Franz Widdershoven
 Jeff Welser
 Philip Wong
 Dirk Wouters
 Kojiro Yagami
 David Yeh
 Hiroaki Yoda
 In-K Yoo
 Victor Zhirnov
Toshiba
Yonsei U.
Sharp
INSIC
GLOBALFOUNDRIES
Seong Kyun Kwan U.
Hanyang U.
IDA
U. Southampton
SNL
SRC
NEC
NICT
NIST
Nantero
INSIC
Intel
JSR Micro
Tokyo Tech
U. Tokyo
Tokyo Inst. Tech.
Rambus
Toyo U.
RWTH A
NXP
NRI/IBM
Stanford U.
IMEC
Sony
SRC/TI
Toshiba
SAIT
SRC
Work in Progress --- Not for Publication
Evolution of Extended CMOS
Elements
Existing technologies
ERD-WG in Japan
New technologies
Beyond CMOS
year
3 ERD
2011 ITRS Summer Conference – San Francisco – July 13, 2011
Changed Scope of Emerging Research
Devices Chapter
♦ New More-than-Moore Section added – Focused on RF
♦ Emerging Research Memory Devices section broadened
in 2011 to include:
 New “Storage Class Memory” Subsection
 New Memory Select Device Subsection
♦ Emerging Research Logic changed
 Transitioned n-InGaAs & p-Ge alternate channel
MOSFETs to PIDS & FEP.
 Synchronized better with the Nanoelectronics
Research Initiative (NRI)
♦ Expanded technology Benchmarking section
♦ Expanded Architecture Section
4 ERD
2011 ITRS Summer Conference – San Francisco – July 13, 2011
2011 ERD Chapter
 Emerging Memory Devices
 Emerging Logic Devices
 More-than-Moore Devices
 Benchmarking and Assessing
Emerging Devices
 Emerging Architectures
5 ERD
2011 ITRS Summer Conference – San Francisco – July 13, 2011
2009 Memory Technology Entries
Resistive Memories
Spin Transfer Torque MRAM
Nanoelectromechanical
Nanowire PCM
Macromolecular (Polymer)
Electronic Effects Memory
− Charge trapping
− Metal-Insulator Transition
− FE barrier effects
6 ERD
Redox Memory
−Electrochemical memory
−Valence change memory
− Fuse/Antifuse (Thermochemical
memory}
Molecular Memory
Capacitive Memory
FeFET Memory
2011 ITRS Summer Conference – San Francisco – July 13, 2011
2011 Memory Technology Entries
Resistive Memories
Spin Transfer Torque MRAM
Nanoelectromechanical
Nanowire PCM
Macromolecular (Polymer)
Electronic Effects Memory
− Charge trapping
− Metal-Insulator Transition
− FE barrier effects
7 ERD
Redox Memory
−Electrochemical memory
−Valence change memory
− Fuse/Antifuse (Thermochemical
memory}
Molecular Memory
Capacitive Memory
FeFET Memory
2011 ITRS Summer Conference – San Francisco – July 13, 2011
ERD/ERM Memory Technology
Assessment Workshop
ITRS ERD/ERM identified two emerging memory
technologies for accelerated research & development:
1) STT-MRAM and 2) Redox Resistive RAM
STT-Memory Cell
8 ERD
Redox Memory Cell
2011 ITRS Summer Conference – San Francisco – July 13, 2011
Memory Hierarchy – Future Memory
Challenge
NVM cost/gigabyte ~ $1
9 ERD
Al Fazio - Intel
2011 ITRS Summer Conference – San Francisco – July 13, 2011
10 ERD
2011 ITRS Summer Conference – San Francisco – July 13, 2011
One Diode – One Resistor (1D1R) Memory Cell
Select Device = Diode
H-S. P. Wong – Stanford U.
11 ERD
2011 ITRS Summer Conference – San Francisco – July 13, 2011
2011 ERD Chapter
 Emerging Memory Devices
 Emerging Logic Devices
 More-than-Moore Devices
 Benchmarking and Assessing
Emerging Devices
 Emerging Architectures
12 ERD
2011 ITRS Summer Conference – San Francisco – July 13, 2011
2009 Logic Technology Tables
Table 1 – Extending
MOSFETs to the End
of the Roadmap
_____________
Table 2- Unconventional
FETS, Charge-based
Extended CMOS
_______________
Table 3 - Non-FET, Non
Charge-based ‘Beyond
CMOS’ devices
_______________
CNT FETs
Graphene nanoribbons
III-V Channel MOSFETs
Ge Channel MOSFETs
Nanowire FETs
Non-conventional
Geometry Devices
Tunnel FET
I-MOS
Spin FET
SET
NEMS switch
Negative Cg MOSFET
Collective Magnetic Devices
Moving domain wall devices
Atomic Switch
Molecular Switch
Pseudo-spintronic Devices
Nanomagnetic (M:QCA)
13 ERD
2011 ITRS Summer Conference – San Francisco – July 13, 2011
2011 Logic Technology Tables
Table 1 – Extending
MOSFETs to the End
of the Roadmap
_______
Table 2- Unconventional
FETS, Charge-based
Extended CMOS
_____________
Spin FET& Spin MOSFET
CNT FETs
Negative Cg MOSFET
Graphene nanoribbons
Atomic Switch
III-V Channel MOSFETs
NEMS switch
Ge Channel MOSFETs
Excitonic FET
Mott FET
Nanowire FETs
Tunnel FET
Tunnel FET
I-MOS
Non-conventional
SET
Geometry Devices
14 ERD
Table 3 - Non-FET, Non
Charge-based ‘Beyond
CMOS’ Devices
_______________
Spin Transfer Torque Logic
Moving domain wall devices
Pseudo-spintronic Devices
Nanomagnetic (M:QCA)
Negative Cg MOSFET
All Spin Logic
Molecular Switch
BiSFET
2011 ITRS Summer Conference – San Francisco – July 13, 2011
ERD/ERM Logic Technology Recommended Focus:
Carbon-based Nanoelectronics – Carbon Nanotubes and Graphene
Conventional Devices
FET
Band gap engineered
Graphene nanoribbons
Graphene quantum dot
(Manchester group)
Nonconventional Devices
Graphene Veselago lense
Cheianov et al. Science (07)
Graphene Spintronics
Graphene pseudospintronics
Son et al. Nature (07)
Trauzettel et al. Nature Phys. (07)
P. Kim – Columbia U.
15 ERD
2011 ITRS Summer Conference – San Francisco – July 13, 2011
2011 ERD Chapter
 Emerging Memory Devices
 Emerging Logic Devices
 More-than-Moore Devices
 Benchmarking and Assessing
Emerging Devices
 Emerging Architectures
16 ERD
2011 ITRS Summer Conference – San Francisco – July 13, 2011
Wireless underlying architecture / functions
rf wave
Higher level function
011001010…
control
LNA
ADC
Intermediate level
function
nanoradio
LO
PA
filter
Lower level functions
DAC
oscillator
mixer
LO
spin-torque oscillator
NEMS nanoresonator
17 ERD
2011 ITRS Summer Conference – San Francisco – July 13, 2011
graphene
17
2011 ERD Chapter
 Emerging Memory Devices
 Emerging Logic Devices
 More-than-Moore Devices
 Benchmarking and Assessing
Emerging Devices
 Emerging Architectures
18 ERD
2011 ITRS Summer Conference – San Francisco – July 13, 2011
Benchmarking
NRI Median Switch Characteristics
1.00E+02
1.00E+01
ENERGY
INV
NAND2
1.00E+00
DELAY
DELAY
ENERGY
AREA
ADD32
AREA
1.00E-01
1.00E-02
All 3 metrics responding consistently – energy and area superiority.
Little change in the energy delay product.
19 ERD
2011 ITRS Summer Conference – San Francisco – July 13, 2011
2011 ERD Chapter
 Emerging Memory Devices
 Emerging Logic Devices
 More-than-Moore Devices
 Benchmarking and Assessing
Emerging Devices
 Emerging Architectures
20 ERD
2011 ITRS Summer Conference – San Francisco – July 13, 2011
Four Architectural Projections
1) Hardware Accelerators execute selected functions
faster than software performing it on the CPU.
2) Alternative switches often exhibit emergent,
idiosyncratic behavior. They also maybe nonvolatile. We should exploit them.
3) CMOS is not going away anytime soon.
4) New switches may improve high utilization
accelerators
21 ERD
2011 ITRS Summer Conference – San Francisco – July 13, 2011
Matching Logic Functions & New Switch Behaviors
New Switch Ideas
Popular Accelerators
Encrypt / Decrypt
Single Spin
Compr / Decompr
Spin Domain
Reg. Expression Scan
Tunnel-FETs
Discrete COS Trnsfrm
NEMS
Bit Serial Operations
H.264 Std Filtering
DSP, A/D, D/A
Viterbi Algorithms
Image, Graphics
?
MQCA
Molecular
Bio-inspired
CMOL
Excitonics
Example: Cryptography Hardware Acceleration
Operations required:
Rotate, Byte Alignment, EXORs, Multiply, Table Lookup
Circuits used in Accel:
Transmission Gates (“T-Gates”)
New Switch Opportunity:
A number of new switches (i.e. T-FETs) don’t have
thermionic barriers: won’t suffer from CMOS Pass-gate
VT drop, Body Effect, or Source-Follower delay.
Potential Opportunity:
Replace 4 T-Gate MOSFETs with 1 low power switch.
22 ERD
2011 ITRS Summer Conference – San Francisco – July 13, 2011
ERD – Key Messages
♦ New More-than-Moore Section added – Focused on RF devices
♦ Emerging Research Memory Devices section broadened in 2011
to include:
 New “Storage Class Memory” Subsection
 New Memory “Select Device” Subsection
 Transitioned STT-MRAM to PIDS & FEP
 Introduced new memory device category – Redox RAM
♦ Emerging Research Logic changes:
 Transitioned n-InGaAs & p-Ge alternate channel MOSFETs
to PIDS & FEP.
 Synchronized more closely with the Nanoelectronics
Research Initiative (NRI)
♦ Expanded technology benchmarking section
♦ Expanded Architecture Section
23 ERD
2011 ITRS Summer Conference – San Francisco – July 13, 2011

similar documents