### Decision Clock Gating Location Constraint Function

```專題製作成果報告
Gated Clock Cloning for Timing Fixing

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Q&A

Constraint Function
Max(Si+Li) + Enable Logic(E0+Ej) + Skew <= Clock
Period (P0) + Delay (Sj)

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Build Kd-tree For Grouping Flip-Flops
Decision Clock Gating Location
Merge Clock Gating
Build Kd-tree For Grouping
Flip-Flops

Decision Clock Gating Location
Constraint Function
Maxdelay(Si+Li) +E0 +Ej+skew<=period+Sj
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Maxdelay(Si+Li)
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Decision Clock Gating Location
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Distance
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clock root 固定置於(0,0)
－Sj = x + y , 先決定Sj再調整Lj
Decision Clock Gating Location
ENABLE
LOGIC
FLIP FLOP
clock root
CLOCK GATE
x + y = Sj
Decision Clock Gating Location
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delay(Lj)的範圍：
Maxdelay-Sj-skew <= Lj <=Maxdelay-Sj
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i1 <= delay(Lj)’s length <= i2
Decision Clock Gating Location
ENABLE
LOGIC
FLIP FLOP
clock root
Lj的範圍
Delay Lj
Lj的範圍
CLOCK GATE
Delay Sj
x + y = Sj
Decision Clock Gating Location
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delay(Lj)的範圍，便重新決定Sj
Decision Clock Gating Location
ENABLE
LOGIC
Delay Ej
FLIP FLOP
clock root
Delay Lj
CLOCK GATE
Delay Sj
x + y = Sj
New
x + y = Sj
Merge Clock Gating
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Bottom-up
FLIP FLOP

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Test case
PERIOD
DIE_SIZE
FLIP_FLOP
case1
4000
8000 x 8000
800
case2
50000
20000 x 15000
1200

Test case
Buffer number
Gate number
Run time
case1
2417
172
1529s
case2
3817
240
804s
Q&A
Thank you
```