Decision Clock Gating Location Constraint Function

Report
專題製作成果報告
Gated Clock Cloning for Timing Fixing
指導教授: 林榮彬教授
專題組員: 韓儩源、蔡萬都
大綱
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問題描述
演算法
流程圖
測試結果
Q&A
問題描述
問題描述
Constraint Function
Max(Si+Li) + Enable Logic(E0+Ej) + Skew <= Clock
Period (P0) + Delay (Sj)
演算法
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Build Kd-tree For Grouping Flip-Flops
Decision Clock Gating Location
Merge Clock Gating
Build Kd-tree For Grouping
Flip-Flops
利用現有的”kdtree algorithm”來對flip-flop
進行nearest neighbor的分堆
Decision Clock Gating Location
Constraint Function
Maxdelay(Si+Li) +E0 +Ej+skew<=period+Sj
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找到一個點是符合skew又不超過
Maxdelay(Si+Li)
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加入Ej檢查Constraint function
Decision Clock Gating Location
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利用提供的查找表來計算delay
距離計算方法:Manhattan
Distance
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clock root 固定置於(0,0)
-Sj = x + y , 先決定Sj再調整Lj
Decision Clock Gating Location
ENABLE
LOGIC
FLIP FLOP
clock root
CLOCK GATE
x + y = Sj
Decision Clock Gating Location
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而從要符合skew的條件下,我們可以得到一個
delay(Lj)的範圍:
Maxdelay-Sj-skew <= Lj <=Maxdelay-Sj
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再利用查找表將Lj的範圍長度算出
i1 <= delay(Lj)’s length <= i2
Decision Clock Gating Location
ENABLE
LOGIC
FLIP FLOP
clock root
Lj的範圍
Delay Lj
Lj的範圍
CLOCK GATE
Delay Sj
x + y = Sj
Decision Clock Gating Location
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加入Ej檢查Constraint function
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若是不符合Constraint function或是找不到
delay(Lj)的範圍,便重新決定Sj
Decision Clock Gating Location
ENABLE
LOGIC
Delay Ej
FLIP FLOP
clock root
Delay Lj
CLOCK GATE
Delay Sj
x + y = Sj
New
x + y = Sj
Merge Clock Gating
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Bottom-up
FLIP FLOP
合併後的group
流程圖
測試結果
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主辦單位測試檔
Test case
PERIOD
DIE_SIZE
FLIP_FLOP
case1
4000
8000 x 8000
800
case2
50000
20000 x 15000
1200
主辦單位測試結果
Test case
Buffer number
Gate number
Run time
case1
2417
172
1529s
case2
3817
240
804s
Q&A
Thank you

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