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module fibonacci_calculator (clk, reset_n, input_s, begin_fibo, fibo_out, done);
input
clk;
input
reset_n;
input
[4:0] input_s;
input
begin_fibo;
output
[15:0] fibo_out;
output
done;
reg
state;
reg
[4:0] count;
reg
[15:0] R0;
reg
[15:0] R1;
parameter IDLE
= 1'b0;
parameter COMPUTE = 1'b1;
assign done = state & (count == 1);
assign fibo_out = R0;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
state <= IDLE;
else case (state)
IDLE:
if (begin_fibo) begin
count <= input_s;
R0 <= 1;
R1 <= 0;
state <= COMPUTE;
end
COMPUTE:
if (count > 1) begin
count <= count - 1;
R0 <= R0 + R1;
R1 <= R0;
end else
state <= IDLE;
endcase
end
endmodule
reset_n clk
module fibonacci_calculator
clocked always statement
5
assign statement
0
Input_s
+1
1
1
+
0
0
R0
1
R1
16
0
state
0
0
1
1
done
fibo_out
16
1
>1
&
5
1
0
==
1
count

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