ASIC 121: Practical VHDL Digital Design for FPGAs

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ASIC 121: Practical VHDL
Digital Design for FPGAs
Tutorial 2
October 4, 2006
Contributions
• I have taken some of the slides in this
tutorial from Jeff Wentworth’s ASIC 120
Combination vs Sequential
• Combinational Logic
– Output only depends on input
– Examples: AND, OR, MUX
• Sequential Logic
– Output depends on inputs and memory
– Examples: State Machine, Counter
Memory
• Two popular ways of implementing
memory:
– Synchronous memory (most popular)
• Uses Flip Flops with a Clock signal
– Asynchronous memory
• Uses Latches
• Much more difficult to design with
Basic Feedback Element: SR latch
S
R
Q Qnext
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0
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N/A
N/A
D Flip-Flop or Register
D
Clk Q Qnext
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0 0
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1 1
0 0
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01
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ASIC 120
• Read through the ASIC 120 Tutorial 2
• Gives a good explanation of state
machines and basic VHDL
Independent Tasks
• All students should have evaluation copies
of Modelsim and Quartus II, if not see
Tutorial 1
Quartus II Exercise
• This exercise builds on the one performed
in Tutorial 1
• Open Quartus II, Select File->New Project
Wizard, Select a valid working directory
(should be an empty folder)
• Name the project and entity “full_adder”
• Click next for all other menus
• Select File->New. Select VHDL File
Quartus II Exercise Cont
•
Save the file as full_adder.vhd, with the contents:
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
Port ( i_X, i_Y, i_Cin : in STD_LOGIC;
o_FA_Sum, o_FA_Cout : out STD_LOGIC
);
end full_adder;
architecture main of full_adder is
Component half_adder
Port ( i_A, i_B
o_Sum, o_Carry
);
end Component;
: in STD_LOGIC;
: out STD_LOGIC
signal carry_1, carry_2, sum_1: STD_LOGIC;
Quartus II Exercise Cont
begin
adder1 : half_adder Port map(
i_A => i_X,
i_B => i_Y,
o_Sum => sum_1,
o_Carry => carry_1);
adder2 : half_adder Port map(
i_A => i_Cin,
i_B => sum_1,
o_Sum => o_FA_Sum,
o_Carry => carry_2);
o_FA_Cout <= carry_1 or carry_2;
end main;
Quartus II Exercise Cont
• Go to Project->Add Files and add the
half_adder.vhd file from Tutorial 1
• You have now seen a hierarchical VHDL
design with multiple files
Quartus II Exercise Cont
• Select Processing->Start->Analysis and
Synthesis
• Make sure it completes successfully
• Next Step
– Read through the help file under “simulation”
– Try Simulating the design
Exercise 2
• Full adders can be chained together into
something called a “ripple adder”
• 3 bit adder (A + B = S):
B2
Carry Out
A2
Full Adder
S2
B1
A1
Full Adder
S1
B0
A0
Full Adder
S0
Carry In
Exercise 2 Cont’d
• Create the architecture description for a 4 bit
ripple adder to implement the entity:
library ieee;
use ieee.std_logic_1164.all;
entity ripple_adder is
port (
A : in std_logic_vector(3 downto 0);
B : in std_logic_vector(3 downto 0);
c_in : in std_logic;
sum : out std_logic_vector(3 downto 0);
c_out : out std_logic
);
end ripple_adder;
VHDL DFF (Flip Flop)
library ieee;
use ieee.std_logic_1164.all;
entity DFF is
port ( d, clk : in STD_LOGIC;
q : out STD_LOGIC
);
end DFF;
architecture main of DFF is
begin
process (clk)
begin
if (clk'event and clk = '1') then
q <= d;
end if;
end process;
end main;

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