test-templates - Embedded Systems

Report
National Sun Yat-sen University
Embedded System Laboratory
A Unified Methodology for Pre-Silicon
Verification and Post-Silicon Validation
Citation : 15
Presenter : Ching-Hua Huang
Adir, A., Copty, S. ; Landa, S. ; Nahir, A. ; Shurek, G. ; Ziv, A. ; Meissner, C. ; Schumann, J.
IBM Res., Haifa, Israel
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
2013/7/15
Abstract
The growing importance of post-silicon validation in
ensuring functional correctness of high-end designs increases the
need for synergy between the pre-silicon verification and postsilicon validation.
We propose a unified functional verification methodology for
the pre- and post-silicon domains. This methodology is based on a
common verification plan and similar languages for test-templates
and coverage models.
Implementation of the methodology requires a userdirectable stimuli generation tool for the post-silicon domain. We
analyze the requirements for such a tool and the differences
between it and its pre-silicon counterpart.
Based on these requirements, we implemented a tool called
Threadmill and used it in the verification of the IBM POWER7
processor chip with encouraging results.
2

Why using Post-silicon validation?
◦ Reasoning
 The size and complexity of modern hardware systems
 Sunk costs
◦ Benefits
 Tests are executed directly on manufactured silicon
 In the past
 Validating electrical aspects
 Diagnosing systematic manufacturing defects
 Today
 Functional validation
◦ Challenges
 Limited internal observability
 Difficult to modify the manufactured chips
3
What’s the problem ? (Cont.)

The growing importance of post-silicon validation
◦ High-end designs increases the need for synergy between the
pre-silicon verification and post-silicon validation.
◦ Propose a unified methodology to building a bridge allowing
easier integration between the domains.

Difference between Pre- and Post-silicon domains
◦ Pre-silicon platforms
 Software simulators and hardware acceleration
 Support detailed level of observability
◦ Post-silicon platforms
 Provide significantly higher execution speeds
 The verification tools need to be adjusted for the best utilization of
available speed
4

5
Pre-silicon verification V.S. Post-silicon validation
Pre-silicon verification
Post-silicon validation
Goal
Finding all the bugs
Finding the bugs that escaped
pre-silicon
Usage Duration
Before tape-out
From prototype silicon to
volume production
Implementation
environment
Virtual platforms
Real-world system boards
Approach
Simulation, Emulation
and Formal verification tools
Logic analyzer and
Assertion-based tools
Speed
Fast
Slow
Observability
Good
Bad
Modifiability
Good
Bad
Time scale
Hours/Days
Weeks / Months
[1]
Functional
verification
Implementation on the
modern hardware systems is
a mammoth task
[2]
Post-silicon
methodology
Post-silicon validation is not a
new idea, but very little is
published on post-silicon
verification methodologies.
[3-7]
Most research in
post-silicon
validation
[13]
Threadmill
The tool that
implemented the
proposed methodology
Unified
Verification
Methodology
Checking and debugging
capabilities of the silicon
platforms
6
[This paper]
[14]
GenesysPro
IBM’s well-established test
generation tool for the
functional verification
Pre-silicon stimuli generation

Motivation
◦ According to the user’s specifications, it can provide
 Desired scenarios
 High-quality test cases

Scenario specifications – test-templates
◦ Test template that defines a scenario (on the left) and a test
generated from this template (on the right).
◦ GenesysPro -IBM’s well-established test generation tool
 Functional verification of processors

7
The generated test cases
◦ Must be valid to the processor’s architecture
◦ Be different from each other as much as possible

Testing knowledge
◦ Defines the interesting verifications events
 Register dependency
 Memory collisions
◦ Employs a reference model
 Simulating on it every generated instruction
Test
Template
Model of the
Architecture
Testing
knowledge
8
Test
Generator
Reference
Model
Test
Test
case
Test
case
case
Simulation
Post-silicon stimuli generation

The first important characteristic
◦ long loading and Initialization time

Exercisers - A self-contained solution
◦
◦
◦
◦
Generates the test-cases
Runs test-cases
Checking
It a good post-silicon solution
 Only loaded once on the DUV

Problem
◦ Simulation speed
 Spend less effort in generating precise interesting scenarios
 Increase in number of tests generated
◦ Low observability
 Overcome this problem by the acceleration platform
9
A unified verification methodology

A key ingredient for the success of such methodology
◦ Providing common languages for the pre- and post-silicon
 Test specification, progress measure, etc.

This verification methodology
◦ Leverages three different platforms:
 Simulation, Acceleration and Silicon
◦ Requires three major components:
 A verification plan
 Directable stimuli generators suited to each platform
 Functional coverage models
 Identifies gaps in the implementation of the plan
10
Threadmill

Threadmill was developed to enable the unified
methodology
◦ To support a verification process by a verification plan
◦ To guide the exerciser through test-templates

Execution process starts with a builder application
◦ Convert the data incorporated in the test-template
◦ The architectural model into data structures that are then
embedded into the exerciser image
Test
Template
Testing
knowledge
Model of the
Architecture
11
Builder
Accelerator
Silicon

Exerciser image is composed of three major
components
◦ A thin, OS-like layer of basic services
◦ A representation of the test-template, architectural model, and
system configuration description
◦ Fixed code that is responsible for the exercising
12
Before the experiment

I think this paper will show the performance of
Threadmill
◦ Because it is the exercise which developed enable the unified
methodology
13
Experimental results

IBM’s POWER7 processor
◦ Implements the 64-bit IBM Power Architecture
◦ POWER7 chip incorporates eight SMT processor cores with
three levels of caches, memory and I/O controllers and other
support and management logic

POWER7 Coverage results
 unit simulation
 core simulation
 EoA : Exercisers on Accelerators
 Fetch unit (IFU) and sequencing unit (ISU)
 EoA is almost similar to the core simulation
14

Conclusions
◦ Random stimuli generator that is controlled via test-templates
◦ The benefits of Threadmill
 Increased synergy between the two domains
 Using a directable generator in post-silicon validation
◦ Incorporate more testing knowledge
 Improve Threadmill to create interesting verification event

My comments
◦ For me, there are many new information and ideas in this
paper.
◦ I still confused in some concept of this paper.
 I will read more reference about this area.
15

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