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Investigating Error Detection using CRC EE800 Project Presentation VISHESH 11089943 Introduction CRC generation is mostly implemented using Linear feedback shift Registers using FlipFlops and XOR gates. But not many understand how to implement a customized parallel CRC circuit described by an arbitrary CRC generator polynomial. In this paper importance of parallel architecture is discussed and how it can be incorporated in different styles so as to compare the number of logic cells used for each Architecture. Serial CRC Implementation USB CRC5 implementation as LFSR using generator polynomial G(x)=x5+x2+1 The problem is that in many cases shift register implementation is suboptimal. It only allows the calculation of one bit every clock. If a design has 16-bit wide data path, meaning that every clock CRC module has to calculate CRC on 16-bit of data, this scheme will not work. Parallel CRC Generator Every clock N bits are processed. M-Bit CRC next state N-Bit Data input Parallel CRC Generator M-Bit CRC Output EXAMPLE OF USB CRC5 with N=4, M=5 @ [1],[2],[5] USB CRC5 with N=4 the parallel CRC equations Mout[0] = Min[1] ^ Min [4] ^ Nin[0] ^ Nin [3] Mout [1] = Min [2] ^ Nin [1] Mout [2] = Min [1] ^ Min [3] ^ Min [4] ^ Nin [0] ^ Nin [2] ^ Nin [3] Mout [3] = Min [2] ^ Min [4] ^ Nin [1] ^ Nin [3] Mout [4] = Min [0] ^ Min [3] ^ Nin [2] Mout is the parallel CRC implementation. #1 CRC DATA(7:0) CRC DATA(7:0)* ERROR NO ERROR #2 CRC DATA(7:0) CRC CRC* DATA(7:0)* ERROR NO ERROR #3 CRC DATA(7:0) CRC CRC* DATA(7:0)* ERROR NO ERROR Example based for #3 0X8041 0X1F 0x8041 0X8261 0XEF ERROR ‘1’ NO ERROR Results Parallel/LUT CRC Generation Block FPGA Data Width Algorithm Stratix EP10S1F672C6 16 CRC-16-USB Stratix EP10S1F672C6 8 Stratix EP10S1F672C6 8 Logic Cells Registers LUT 86 32 54 CRC-16-USB 22 16 6 CRC-16-USB 81 0 81 Comparison CRC CRC DATA(7:0) DATA(7:0)* ERROR NO ERROR CRC DATA(7:0) CRC CRC* DATA(7:0)* ERROR NO ERROR References [1] G. Campobello, G Patane, M Russo, “Parallel CRC Realization” (http://ai.unime.it/~gp/publications/full/tccrc.pdf) [2] G.Albertango and R. Sisto, “Parallel CRC Generation”, IEEE Micro, Vol. 10, No. 5, October 1990, pp. 63-71. [3] A. Perez, “Byte-wise CRC Calculations”, IEEE Micro, Vol. 3, No. 3, June 1983, pp. 40-50 [4] Adrian Simionescu, Nobug Consulting http://space.ednchina.com/upload/2008/8/27/5300b83c-43ea-459b-ad5c-4dc377310024.pdf [5]Evgeni Stavinov, 2010 issue of Circuit Cellar magazine, Page 40. [6] R. J. Glaise, “A two-step computation of cyclic redundancy code CRC-32 for ATM networks”, IBM Journal of Research and Development Volume 41 , Issue 6 (November 1997) pp 705 - 710 THANK YOU