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The ARM Microcontroller
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ARM Ltd
• Founded in November 1990
– Spun out of Acorn Computers
• Designs the ARM range of RISC processor
cores
• Licenses ARM core designs to semiconductor
partners who fabricate and sell to their
customers.
– ARM does not fabricate silicon itself
• Also develop technologies to assist with the
design-in of the ARM architecture
– Software tools, boards, debug hardware,
application software, bus architectures,
peripherals etc
HISTORY
• 1995: Introduction of Thumb and ARM8.
• 1996 – 2000: Alcatel, Huindai, Philips, Sony, use ΑRM, while in
1999 η ARM cooperates with Erickson for the development of
Bluetooth.
• 2000 – 2002: ARM’s share of the 32 – bit embedded RISC
microprocessor market is 80%. ARM Developer Suite is
introduced.
ARM
System - On - Chip Architecture
3
HISTORY
• 1985: Acorn Computer Group manufactures the
first commercial RISC microprocessor.
• 1990: Acorn and Apple participation leads to the
founding of Advanced RISC Machines (A.R.M.).
• 1991: ARM6, First embeddable RISC
microprocessor.
• 1992 – 1994: Various companies use ARM (Sharp,
Samsung), while in 1993 ARM7, the first
multimedia microprocessor is introduced.
PREREQUISITES
• Before studying ARM, we should be familiar
with the following terms.
I. Context switching
II. Exception handling
III. Data alignment
IV. Watchdog timer
V. Barrel shifter
VI. CISC and RISC
CONTEXT SWITCHING
• Context is basically the state or situation of
any particular event .when this word is used in
technical terms then it refers to the state of
the instruction or thread or task or any mode.
• Context switching can be defined as the
storing of the current state of any thread to be
performed at a later stage.
WHY TO SWITCH?
• Context switching is done for the better
efficiency of the execution. Context switching
comes into play in a condition when the need
for the immediate change of mode or process
occurs. For such condition we are required to
save the current status of the ongoing
process, so that we can access this data later
after the immediate chance in successfully
served.
DATA ALIGNMENT
• Data alignment refers to the storage of data at a
location from where it takes the minimum number of
operation cycles for the processor to read the data.
The task execution process in a processor is basically
divided into two parts; reading/writing the data and
processing the data. And generally speaking,
reading/writing the data is responsible for the
majority portion of the time taken in task execution.
Therefore, if data is properly aligned in the memory
device then the time taken for the execution of the
task is reduced to a great extent.
DATA ALIGNMENT IN ARM
WATCHDOG TIMER
• Watchdog timer is a device that is used to
prevent the system from false functioning. This
WDT trigger various kind of command to protect
system from committing error. All such act that a
WDT executes in order to safeguard the system
from doing any mistake are known as Corrective
measures. Along with correcting the error, this
device also work on the detection of the fault in
the system.
MECHANISM OF WATCHDOG TIMER
• When system is working properly then the watchdog
timer remains in the started state.
• Mechanism of watchdog timer is done by an ON-OFF
action. Its mechanism works in following ways:• As soon as any external action, fault on any internal
flow turns on and watchdog timer off then the
watchdog timer will elapse and procedure a timeout
signal .this timeout will enable the correction action
to move the system in safe mode
EXCEPTION HANDLING
• The ARM architecture supports a range of interrupts,
traps and supervisor calls, all grouped under the general
heading of exceptions. The general way these are
handled is the same in all cases:
• The current state is saved by copying the PC into rl4_exc
and the CPSR into SPSR_exc (where exc stands for the
exception type).
• The processor operating mode is changed to the
appropriate exception mode.
• The PC is forced to a value between 0016 and 1C16, the
particular value depending on the type of exception.
WHY DOES IT OCCUR?
• Atomic instructions are long and complex set
of instructions and hence they use various
shared resources for long operation cycles.
Since we know that if a single resource is
accessed by multiple tasks at the same time
then it can produce false results in both the
tasks, therefore we keep the interrupt signal
disabled during the execution of an atomic
instruction.
CISC
• CISC is a self explanatory term that works
towards making the instruction more complex
in order to reduce the semantic gap lying
between the instruction and machine codes.
This complex instruction is a sequence of
numerous critical operations. And hence
number of clock cycles is taken for the
execution of one single instruction.
RISC
• The concept of RISC came in 1980 by Patterson and
Ditzel which was further supported by Berkely.
Berkely gave the design of RISC I over CISC processor
which has high performance level. Early RISC
projects: IBM 801 (America), Berkeley SPUR, RISC I
and RISC II and Stanford MIPS.
FEATURES OF RISC
• 1.RISC execute a instruction in one cycle and it has a
fixed instruction length of 32 bit while in the case of
CISC it has variable instruction length of different
format and it take several cycle to execute a
instruction.
• RISC uses pipelining technique. In pipelining two or
more instruction is been executed at a time and this
improve the utilization of the hardware resources. A
less of pipelining is used in CISC.
BARREL SHIFTER
• A barrel shifter is a digital circuit that can shift
a data word by a specified number of bits in
one clock cycle. It can be implemented as a
sequence of multiplexers (mux.), and in such
an implementation the output of one mux is
connected to the input of the next mux in a
way that depends on the shift distance.
SCHEMATIC OF SHIFTER
Using the Barrel Shifter:
The Second
Operand
Register,
optionally with shift operation
Operand
1
Operand
2
– Shift value can be either be:
• 5 bit unsigned integer
• Specified in bottom byte of another
register.
– Used for multiplication by constant
Barrel
Shifter
Immediate value
– 8 bit number, with a range of 0-255.
• Rotated right through even number of
positions
ALU
Result
– Allows increased range of 32-bit
constants to be loaded directly into
registers
DATA SIZES AND INSTRUCTION SETS
• The ARM is a 32-bit architecture.
• When used in relation to the ARM:
– Byte means 8 bits
– Half word means 16 bits (two bytes)
– Word means 32 bits (four bytes)
• Most ARM’s implement two instruction sets
– 32-bit ARM Instruction Set
– 16-bit Thumb Instruction Set
• Jazelle cores can also execute Java bytecode
The ARM Register Set
Current Visible Registers
Abort
Mode
SVC
Undef
Mode
Mode
IRQ
FIQ
User
Mode
Mode
Mode
r0
r1
r2
r3
r4
r5
Banked out Registers
r6
r7
r8
r9
r10
r11
User
FIQ
IRQ
SVC
Undef
Abort
r8
r9
r10
r11
r8
r9
r10
r11
r12
r13 (sp)
r12
r13 (sp)
r12
r13 (sp)
r13 (sp)
r13 (sp)
r13 (sp)
r13 (sp)
r14 (lr)
r15 (pc)
r14 (lr)
r14 (lr)
r14 (lr)
r14 (lr)
r14 (lr)
r14 (lr)
spsr
spsr
spsr
spsr
spsr
cpsr
spsr
Register Organization Summary
User
r0
r1
r2
r3
r4
r5
r6
r7
FIQ
User
mode
r0-r7,
r15,
and
cpsr
r8
r9
r10
r11
r12
r13 (sp)
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r15 (pc)
IRQ
User
mode
r0-r12,
r15,
and
cpsr
SVC
User
mode
r0-r12,
r15,
and
cpsr
Undef
User
mode
r0-r12,
r15,
and
cpsr
Abort
User
mode
r0-r12,
r15,
and
cpsr
Thumb state
Low registers
Thumb state
High registers
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
spsr
spsr
spsr
spsr
spsr
cpsr
Note: System mode uses the User mode register set
The Registers
• ARM has 37 registers all of which are 32-bits long.
–
–
–
–
1 dedicated program counter
1 dedicated current program status register
5 dedicated saved program status registers
30 general purpose registers
• The current processor mode governs which of several banks is accessible.
Each mode can access
–
–
–
–
a particular set of r0-r12 registers
a particular r13 (the stack pointer, sp) and r14 (the link register, lr)
the program counter, r15 (pc)
the current program status register, cpsr
Privileged modes (except System) can also access
– a particular spsr (saved program status register)
Program Status Registers
31
28 27
NZCVQ
f
•
23
J
16 15
8
N = Negative result from ALU
Z = Zero result from ALU
C = ALU operation Carried out
V = ALU operation oVerflowed
•
•
•
– Architecture 5TEJ only
– J = 1: Processor in Jazelle state
5
4
0
Interrupt Disable bits.
T Bit
– Architecture xT only
– T = 0: Processor in ARM state
– T = 1: Processor in Thumb state
Sticky Overflow flag - Q flag
J bit
6
– I = 1: Disables the IRQ.
– F = 1: Disables the FIQ.
– Architecture 5TE/J only
– Indicates if saturation has occurred
•
7
I F T mode
c
U n d e f i n e d
s
x
Condition code flags
–
–
–
–
•
24
Mode bits
– Specify the processor mode
Program Counter (r15)
• When the processor is executing in ARM state:
– All instructions are 32 bits wide
– All instructions must be word aligned
– Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as
instruction cannot be halfword or byte aligned).
• When the processor is executing in Thumb state:
– All instructions are 16 bits wide
– All instructions must be halfword aligned
– Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as
instruction cannot be byte aligned).
• When the processor is executing in Jazelle state:
– All instructions are 8 bits wide
– Processor performs a word access to read 4 instructions at once
Exception Handling
• When an exception occurs, the ARM:
– Copies CPSR into SPSR_<mode>
– Sets appropriate CPSR bits
• Change to ARM state
• Change to exception mode
• Disable interrupts (if appropriate)
– Stores the return addr LR_<mode>
– Sets PC to vector address
• To return, exception handler needs
– Restore CPSR from SPSR_<mode>
– Restore PC from LR_<mode>
This can only be done in ARM state.
0x1C
0x18
0x14
0x10
0x0C
0x08
0x04
0x00
FIQ
IRQ
(Reserved)
Data Abort
Prefetch Abort
Software Interrupt
Undefined Instruction
Reset
Vector Table
Vector table can be at
0xFFFF0000 on ARM720T
and on ARM9/10 family
devices

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