Base System Builder

Base System Builder
• Reference web site
Launch Xilinx Platform Studio
Select Base System Builder to create a new design
Enter a path for your project
• Two key requirements:
-The project file must be named 'system.xmp'
-The project file must be saved to a folder with no spaces in its path
- "C:\Documents and Settings\user\" will not work!
Choose the option for a new design.
Select Board
• Select WARP Kits (FPGA/Clock/Radio Boards)
and FPGA v2.2 / Radio 1.4 / Clock 1.1.
Select Processor
• The Xilinx EDK supports two embedded processors. The PowerPC
processor is a "hard" processor core, embedded in the fabric of the Virtex4 FPGA on the WARP FPGA board
Configure PowerPC Processor
Configure IO Interface
- warp_v4_userio_all
- rs232_db9
- clock_board_config
- radio_bridge_slot_2
- radio_controller_0
- rs232_usb (a second serial port that is converted to USB on the board using an
FTDI chip)
- sysace_compactflash
- TriMode_MAC_GMII
- radio_bridge_slot_1
- radio_bridge_slot_3
- radio_bridge_slot_4
- eeprom_controller
- analog_bridge_slot_4
- user_io_board_controller_slot1
Configure IO Interface
Software Setup
System Created

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