Unit-2 - KIT – ECE

Report
ECEA
STICK DIAGRAMS
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VLSI design aims to translate circuit concepts onto
silicon
stick diagrams are a means of capturing topography
and layer information - simple diagrams
Stick diagrams convey layer information through color
codes (or monochrome encoding)
Stick Encoding
Layer
Thinox
Polysilicon
Metal1
Contact cut
NOT applicable
Overglass
Implant
Buried contact
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Mask Layout Encoding
Stick Encoding
Layer
P-Diffusion
Not Shown in Stick Diagram
P+ Mask
Metl2
VIA
Demarcation Line
P-Well
Vdd or GND CONTACT
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Mask Layout Encoding
For reference : an nMOS Inverter coloured stick diagram
* Note the depletion mode device
Vdd = 5V
Vout
Vin
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CMOS Inverter coloured stick diagram
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Stick diagram -> CMOS transistor circuit
Vdd = 5V
Vdd = 5V
pMOS
Vout
Vin
nMOS
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Vin
Vout
All paths in all layers will be dimensioned
in λ units and subsequently λ can be
allocated an appropriate value compatible
with the feature size of the fabrication
process.
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Thinox
n-diffusion
Metal 1
p-diffusion
3λ
2λ
3λ
2λ
2λ
2λ
λ
Minimum distance rules between device3layers,
e.g.,
• polysilicon  metal
• metal  metal
Metal 2
• diffusion  diffusion and
2λ
• minimum layer overlaps
are used during layout
4λ
3λ
4λ
Polysilicon
4λ
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nMOS transistor mask representation
gate
polysilicon
source
drain
metal
Contact holes
diffusion (active
region)
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Contact Cuts
• Three possible approaches –
1. Poly to Metal
2. Metal to Diffusion
3. Buried contact (poly to diff) or butting
contact (poly to diff using metal)
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Layout Design rules & Lambda ()
2
• Minimize spared diffusion
• Use minimum poly width (2)
•Width of contacts = 2
•Multiply contacts
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Layout Design rules & Lambda ()
3
6
6
2
2
All device mask dimensions are based on multiples of , e.g., polysilicon minimum
width = 2. Minimum metal to metal spacing = 3
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Layout Design rules & Lambda ()
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CMOS Layout
N Well
P diff
Contacts
Poly
N diff
P Substrate
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Metal
Layout Design rules & Lambda ()
Width of pMOS
should be twice the
width of nMOS
• L min
• Wpmos=2 Wnmos
• Same N and P alters symmetry
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Lambda Based Design Rules
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Design rules based on single parameter, λ
Simple for the designer
Wide acceptance
Provide feature size independent way of setting out mask
Minimum feature size is defined as 2 λ
Used to preserve topological features on a chip
Prevents shorting, opens, contacts from slipping out of area to
be contacted
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CMOS Inverter Mask Layout
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CMOS Layout Design
• CMOS IC are designing using stick diagrams.
• Different color codes for each layer.
• Lamda/micron grid.
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CMOS AN2 (2 i/p AND gate) Mask Layout
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nMOS Inverter coloured stick diagram
* Note the depletion mode
device
Vdd = 5V
Vout
Vin
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Two-way selector with enable
X
off
on
A
Y
off
on
off
on
E
A’
E=0
A=0|1
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Static CMOS NAND gate
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Static CMOS NOR gate
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Static CMOS Design Example Layout
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Layout 2 (Different layout style to previous but same function being implemented)
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Complex logic gates layout
• Ex—F=AB+E+CD
• Eulerpaths
• Circuit to graph (convert)
1) Vertices are source/Drain connections
2) Edges are transistors
• Find p and n Eulerpaths
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VirtuosoFab
Touch the deep submicron technology
• 3D fabrication process simulator with cross
sectional viewer.
• Step-by-step 3-D visualization of fabrication
for any portion of layout.
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2D Cross Section
NMOS Transistor
Metal Layer
Contacts
Poly
N Diffusion
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