Lecture 10

Report
CENG 241
Digital Design 1
Lecture 10
Amirali Baniasadi
[email protected]
This Lecture
 Review of last lecture: Analysis
 Chapter 5: State Reduction, Design Procedure
2
Analysis of Clocked Sequential Circuits
 Analysis: Obtaining a table/diagram for the time sequence of
inputs/outputs/internal states.
 Examples: State Equations, State Table, State Diagram
3
Analysis of Clocked Sequential Circuits
Example of state equation:
A(t+1) = A(t)x(t) + B(t)x(t)
B(t+1) = A’(t)x(t)
A(t+1)=Ax+Bx
B(t+1)=A’x
y(t)=(A(t)+B(t)).x’(t)
= (A+B)x’
4
Example of state tables
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Present
A
0
0
0
0
1
1
1
1
state
B
0
0
1
1
0
0
1
1
input
x
0
1
0
1
0
1
0
1
Next State
A
B
0
0
0
1
0
0
1
1
0
0
1
0
0
0
1
0
Output
y
0
0
1
0
1
0
1
0
State equation:
A(t+1) = A(t)x(t) + B(t)x(t)
B(t+1) = A’(t)x(t)
y(t)=(A(t)+B(t)).x’(t)
5
Example of state tables-2nd form
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Present state
AB
00
01
10
11
Next State
x=0
x=1
AB
AB
00
01
00
11
00
10
00
10
Output
x=0
x=1
y
y
0
0
1
0
1
0
1
0
State equation:
A(t+1) = A(t)x(t) + B(t)x(t)
B(t+1) = A’(t)x(t)
y(t)=(A(t)+B(t)).x’(t)
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Example of state diagram
Present state
AB
00
01
10
11
Next State
x=0
x=1
AB
AB
00
01
00
11
00
10
00
10
Output
x=0 x=1
y
y
0
0
1
0
1
0
1
0
7
Mealy & Moore
 Mealy machine: Output depends on both input & present state
 Moore machine: Output only depends on present state.
8
Example of Mealy Machine
Present state
AB
00
01
10
11
Next State
x=0
x=1
AB
AB
00
01
00
11
00
10
00
10
Output
x=0 x=1
y
y
0
0
1
0
1
0
1
0
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Example of Moore Machine
Present state
A
B
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
input
x
0
1
0
1
0
1
0
1
Next State
A
B
0
1
0
0
1
1
1
0
1
1
1
0
0
0
1
1
10
State Reduction and Assignment
 Goal: Reduce the number of states while keeping the external input-output
requirements.
 2m states need m flip-flops, so reducing the states may reduce flip-flops.
 If two states are equal, one can be removed but what are equal states?
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State Reduction Example
As an example consider the input sequence below:
010101110100 applied and start from state a.
State
input
output
a a b c d e f f g f g
0 1 0 1 0 1 1 0 1 0 0
0 0 0 0 0 1 1 0 1 0 0
a
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State Reduction Example
Present State
a
b
c
d
e
f
g
Next State
x=0
x=1
Output
x=0
x=1
a
c
a
e
a
g
a
0
0
0
0
0
0
0
b
d
d
f
f
f
f
0
0
0
1
1
1
1
States e and g are equal since for each member of the set of
inputs, they give the same output and send the circuit either to
the same state or an equivalent state.
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State Reduction Example
Present State
a
b
c
d
e
f
Next State
x=0
x=1
Output
x=0
x=1
a
c
a
e
a
e
0
0
0
0
0
0
b
d
d
f
f
f
0
0
0
1
1
1
NEW equal states: d and f
Table and state diagram after the first reduction: g is removed and replaced by state e.
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State Reduction Example
Present State
a
b
c
d
e
Next State
x=0
x=1
Output
x=0
x=1
a
c
a
e
a
0
0
0
0
0
b
d
d
d
d
0
0
0
1
1
If we apply the same sequence
State
input
output
a a b c d e d d e d e
0 1 0 1 0 1 1 0 1 0 0
0 0 0 0 0 1 1 0 1 0 0
a
Table and state diagram after the second reduction: f is removed and replaced by state d.
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Design Procedure
First Step: From the word description of the problem derive a state diagram
example:design a circuit to detect three or more consecutive 1’s in a string of bits
coming through an input line.
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Design steps
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1.From word description, derive state diagram
2.Reduce the number of states
3.Assign binary values to states
4.Obtain the binary coded state table
5.Choose the type of flip-flop used
6.Derive the simplified flip-flop input and output equations
7.Draw the logic diagram
 steps 4 to 7can be implemented by exact algorithms and can be
automated.
 The part of the design that is well-defined is referred to as synthesis.
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State Table for Sequence Decoder
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Present State
A
B
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Input
x
0
1
0
1
0
1
0
1
Next State
A
B
0
0
0
1
0
0
1
0
0
0
1
1
0
0
1
1
Output
y
0
0
0
0
0
0
1
1
A(t+1)= Σ(3,5,7)
B(t+1)= Σ(1,5,7)
Y(A,B,x)= Σ(6,7)
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Synthesis Using D Flip-Flops
A(t+1)=DA(A,B,x)= Σ(3,5,7)
B(t+1)=DB(A,B,x)= Σ(1,5,7)
Y(A,B,x)= Σ(6,7)
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Logic Diagram for a Sequence Detector
DA = Ax + Bx
DB= Ax + B’x
y=AB
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Excitation Tables
 Using flip-flops other than D can be complicated.
 Why? Input equations for the circuit must be derived indirectly from the
state table
 Excitation tables can help.
 Excitation tables give us the flip-flop input for every state transition.
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Example : JK- Recall Q(t+1) = JQ’(t) + K’Q(t)
Q(t)
Q(t+1)
J
K
0
0
0
X
0
1
1
X
1
0
X
1
1
1
X
0
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Excitation Tables- T flip-flop
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Example : JK- Recall Q(t+1) = TQ’(t) + T’Q(t) = T XOR Q
Q(t)
Q(t+1)
T
0
0
0
0
1
1
1
0
1
1
1
0
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Synthesis Using JK Flip-Flops
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Present State
A
B
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Input
x
0
1
0
1
0
1
0
1
Next State
A
B
0
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
JA
0
0
1
0
x
x
x
x
Flip-Flop Inputs
KA
JB
x
0
x
1
x
x
x
x
0
0
0
1
0
x
1
x
KB
x
x
1
0
x
x
0
1
 We also include J, K input conditions, derived from the excitation
table.
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Synthesis Using JK Flip-Flops
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Synthesis Using JK Flip-Flops
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Synthesis Using T Flip-Flops
Example: 3-bit Binary Counter
The counter counts the clock.
Clock does not appear explicitly in the state diagram.
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Synthesis Using T Flip-Flops
Present State
A2 A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
A2
0
0
0
1
1
1
1
0
Next State
A1
A0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
Flip-Flop Inputs
TA2
TA1
TA0
0
0
1
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
0
1
1
1
1
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Synthesis Using T Flip-Flops
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Synthesis Using T Flip-Flops
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Summary
 State Reduction, Synthesis
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