SoC 기술의 현재와 미래

Report
SoC 기술의 현재와 미래
2003. 3. 7
경 종민
목차
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1.
2.
3.
4.
5.
6.
반도체 제조 기술의발전
Embedded System 의 출현, 확산
Future Opportunity through SoC
각 나라의 SoC 개발전략과 현황
Major Issues/Challenges of SoC
한국의 SoC 설계 기술의 발전 전략
Advent of SoC; Its Background
• Handling of Information, 작게 만드는 능
력 ; enabled by Silicon Technology
• 큰 시스템을 설계하는 능력 ; enabled by
Hierarchy, Encapsulation,
Standardization and Platform-based
approach
반도체 제조 기술의 발전
Foundry
• Leading-edge platform
–
–
–
–
–
–
0.13 and 0.10 micron
Copper interconnect
True Low-K dielectric
Mixed Mode and RF
Embedded DRAM
High Speed IO
• Time-to-Market and Volume production
• Solution and Service Oriented Environment
– Library, IP, EDA tool, and Design Kit
• Cost Effective Manufacturing
• Long Term Partnership
Evolution of silicon technology
1997
1998
1999
2002
0.35
0.25
0.18
0.13
Cost of fab (billion $)
1.5~2.0
2.0~3.0
3.0~4.0
4.0+
Design cycle (month)
18~12
12~10
10~8
8~6
Derivative cycle (month)
8~6
6~4
4~2
3~2
Silicon complexity (gate)
200~500K
1~2M
4~6M
10~25M
Cellular,
Set-up
Internet
Ubiquitous
PDA,DVD
box,
appliances,
computing
Wireless
portables
Process technology (u)
Applications
PDA
Primary IP reuse
intragroup
intergroup
intercompany
Intercompany,
interindustry
Source: Surviving the SOC revolution –
H.Chang et.al.
Projected trend
1999
2001
2003
2006
2009
2012
140
120
100
70
50
30
0.256
1
1
4
4
64
2000/975
2400/1195
3000/1460
4000/1970
5400/2655
7300/3585
1.25
1.50
2.1
3.5
6.0
10.0
Chip size (uP/DRAM;m2)
340/400
385/445
430/560
520/790
620/1120
750/2580
Power supply (V)
1.5~1.8
1.2~1.5
1.2~1.5
0.9~1.2
0.6~0.9
0.5~0.6
90
110
130
160
170
175
MPU gate length (nm)
DRAM (GB)
I/O pin
On-chip clock (GHz)
Power (W)
0.13 um Technology Highlights
- compared to 0.18um
• 0.13 Technology with Copper and Low K(2.7) dielectric passed
pilot production Qualification in Q1, 2001.
– Pilot run, general customer, silicon shuttle, Library : Already
available
– About 50 customer products already design-in for this technology.
• Layout density increases by about 50%
• Device performance increases by more than 50%
– Inverter delay : 11.5ps(0.10um) vs. 14ps(0.13um) vs. 27ps(0.18um)
for standard HS device
•
Cu interconnect with low K–dielectric constant reduces from
3.6(FSG) to 2.7(SiLK)
– 25 – 30 % improvement of RC delays
– **** Reduce coupling capacitance by 25% *****
Technology Scaling Trend
• Scaling of x0.7 every years
– 0.25um 0.18um 0.13um 0.10um 0.07um 0.05um
– 1997
1999
2002
2005
2008
2011
– 5LM
6LM
7LM
7LM
8LM
9LM
• Interconnect delay dominates system performance
– Consumes 70% of clock cycle
• Aggressive pitch & aspect ratio
–
–
–
–
Cross coupling capacitance is dominating
Cross capacitance  100%, ground cap  0%
90% in 0.18um
Harms in signal integrity, cross-talk, noise
• Interconnect optimization
– optimal pitch(width+spacing)
– Shielding,
– repeater, buffering
New Materials Implications
• Lower dielectric
– Reduce total capacitance
• Copper metalization
– Reduce RC delay
– Avoid electromigration
– Thinner deposition reduces cross coupling
capacitance
• Multi layers of routing
– Relative routing pitch may increase
– Room for shielding
Technical Issues in DSM design
• Manufacturability (chip can’t be built)
–
–
–
–
–
Antenna rules
Density rules
Minimum area rules for stacked vias
CMP(Chemical mechanical polishing) area fill rules
Layout correction for optical proximity effects in
subwavelength lithography, associated verification issue
• Signal Integrity(failure to meet timing targets)
– Crosstalk induced errors
– Timing dependent on crosstalk
– IR drop on power supply
• Reliability ( design failures in the field)
– Electromigration on power supply
– Hot electron effect on device
– Wire self heat effect on clock and signals
Embedded System 의 확산
Why Embedded System?
• 민주화, 자유화, 이동성 증대에 따른 개인의 권
리, 자산의 상대적 증가 ; Volume market driven
by individual consumers (100 ~ 1000 dollar
items)
• CMOS silicon 기술 발전의 놀라운 지속성 ;
Lowered cost of localized information
processing, storage plus RF, 통신 인프라 에
의한 연결성(Connectedness)의 확보
• Software(OS, API)에 의한 유연성, 확장성
Embedded System 의 정의
• Definition; 더 큰 시스템 안에서 주어진 특
정한 task 를 수행하기 위하여 삽입된 시스
템으로서, 대개 software(혹은 firmware)
와 hardware 로 구성되며, processor
core 를 포함하는 SoC(System on a Chip)
으로 구현된다.
• Example; 비행기내의 자동항법장치, IMT
2000 단말기칩, 자동차내의 ABS(Antilock Braking System), Smart Card 칩…
Embedded System 의 특징
• vs. 범용 시스템; 성능우수, 양산시 원가하강, 크기,전력
등 이점 있슴.
• vs. Off-line(Detached) System; real-time(응답시간),
reactive(raw data, 즉 analog 신호, 기계/화학/물리 신
호를 처리), multi-rate, multi-level 신호내재,
criticalness(고장시 피해정도) 큼.
• vs. Centralized(External Server) System; Computing
cost 가 communication cost 에 비해 급속 하락하므로
정보처리를 local 에서 처리하는 것이 유리해 짐.
• vs. Special(Fixed) Hardware; 최적화된 processor
core(많은 설계 비용이 집중 투자됨)와
firmware(software) routine 제공, 갱신성 우수,
ES 설계작업의 애로사항
• Verification 과 Testing 이 복잡하고 어렵다.(실제 상황,
즉 주변 시스템을 구현해야 하는 점, 또 여기서 실제 나
타나는 여러 형태의 실제 신호의 관찰, 제어가 어려움등.)
• 개발환경이 PC 나 Workstation 에 비해 열악함.(Library,
debugging tools…)
• Specification 부터 구현까지 한 눈으로 보는 사람이 있
거나, 전체 design flow 가 각 팀간에 긴밀히 이루어져야
함.
• 모제품의 수명이 짧아서, 허용되는 설계기간(design
turn-around) 가 짧다.
• 분야간(예; HW 와 SW), 과정간(예; spec 작업과 설계,
검증, 제작과정), 팀간(예;팀의 위치, 담당블록) 동시공학
(Concurrent Engineering) 의 도입이 필요함.
ES 의 설계시 주요 쟁점
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동작 속도
소모 전력(standby, operating power)
updatability(programmability)
Size, weight
Pin count, IO type, package type
Cost(NRE, production cost)
Development time
Market size and duration, competitors, leader’s
advantage(inertia)
• Associate supplies and materials(development
system, simulator/debugger, SW/FW libraries)
• Production channel 의 안정성(IP, foundry, SW library,
EDA tools, layout/test/package service…)
• User interface
ES 설계 과정
•
•
•
•
•
1. Identify Requirements.
2. Extract Specifications.
3. Decide/Choose/Build Architecture.
4. Select Components.
5. Integrate/Evaluate/Iterate if
necessary.
ES 의 전망
• ES 의 유일한 경쟁력 있는 구현방식은
SoC 임.
• 가장 큰 IT 시장을 형성할 것임. (SoCbased ES 가 cost, performance, update,
TTM, reliability 면에서 탁월)
• Inertia 가 큼(Entry barrier, membership
premiun 큼; 개발 기간이 길고, 과정이 복
잡함. 또한, Target system 과의 연동성,
위험부담 공유 등 때문)
Future Opportunities
through SoC
What is SoC??
• Printed Circuit Board vs. Silicon board
P
RTL
ROM
Netlist
vs.
• Design Reuse  Use IP !!
• Design Specification  Use C Language !!
• Verification Methodology  In-System Verification !!
Advent of SOC
• Growing design productivity gap between gate
density (58%/Y) and designer productivity (21%/Y)
• Shrinking Time-To-Market (narrow market window)
• Viable solution  Design Reuse
PCS
PCs
Color TV Cable TV
Cellular
VCRs
DVB
Black &
White TV
DVD
1
million
Units
5
International Technology Roadmap
For Semiconductors 1999 Ed.
- Semiconductor Industry Association
10
15
Wireless Communications Report, BIS, Boston,
1995+ Dataquest
20 years
Evolution of reuse
Until early 80’s
80’s-90’s
Late 90’s –
TTL/MSI
Reuse of Tr.
ASIC/ASSP
Reuse of Gates
System-on-chip
Reuse of
Socketized IP
Hard component
from A company
Hard component
from B company
Virtual component
from C company
Virtual component
from D company
Design methodology & reuse model
Plug & play SOC
Complex ASIC
with a few IPs
uP
Core
ASIC on DSM
SW I/F IP
Timing-driven design (TDD)
Personal
Reuse
Designerspecific
reuse practices
Retaining
key personnel
FLASH
Logic
Logic
Area Driven
SRAM
Block-based design (BBD)
Source
Reuse
Functional
starting
points for block
design
Document,
testbench,
predictability
Opportunistic IP Reuse
SRAM
uP
Core
FLASH
D-Cache
USB
MPEG
FIFO
SRAM
Logic
Platform-based design (PBD)
Core
Reuse
Virtual
Component
Reuse
Predictable,
Pre-verified,
Core function
Socketized
Functions for
Plug & Play
integration
Firm/hard IP
Planned IP Reuse
Adopted from ‘Surviving the SOC
revolution’ by H. Chang et.al.
• Why SoC(merit) ;
– 더 많은 기능과 성능을 한 칩 안에 구현하는 것을
집적(integration)이라 한다. 그러면 집적도의 증가
가 주는 장점은 무엇인가?
• 면적, 무게가 준다(경·박·단·소)
• 동작속도가 빨라진다. 손목 TV, IMT 2000 단말기
• 가격이 싸진다.
• 신뢰성이 높아진다. 즉, 부품간의 연결이 외부와 차단된
칩 안에서 이루어지므로 불량(제조시, 사용중)이 적다.
– (반도체 기술의 발전 : 무어의 법칙) 지난 30여년간
집적도 즉, 제조기술은 꾸준히 향상되었다.
– (시장요구의 다변화와 제품 cycle의 단축) 그러나,
설계 생산성이 그에 따라가지 못하게 되어, 시장이
요구하는 기능의 제품을 시장이 원하는 TTM(Timeto-Market) 이내의 시간에 만들지 못하게 되었다.
– SoC는 서로 다른 설계자에 의해 설계되고 검증된 여러
기능 블록(IP : Intellectual Property)을 재사용함으로써
(design reuse) 설계 생산성을 높혀주는 새로운 패러다
임의 설계 및 구현방식이다.
개발시간
(TTM)
9 month(TTM critical)
IP reuse
SoC
칩의 복잡도
1) SoC Comprises(Structure) ;
• 디지털 처리 : -processor, -controller, digital
logic, field-programmable logic
• 저장 : memory(ROM, SRAM, DRAM, flash)
• 형태변환 : A/D, D/A
• 입출력 : driver/buffer, I/F controller
• 전원 : power control/supply
• 아날로그 처리 : analog 회로
• 무선 : rf transceiver
• MEMS : sensor/actuator
• Platform : bus controller
2) SoC performs(sub-fuction) ;
Signal processing / computing /
conversion / storage / en-decoding /
cryptography / communication / housekeeping / using RTOS, firmware, software,
hardwired logic, mixed-signal circuit, rf
circuit and MEMS/Sensor
3) SoC comes from(needed expertise) ;
Architecture/algorithm 설계
시스템설계
HW/SW 동시설계(simulation, 검증)
디지털
엔지니어,
소프트웨어
엔지니어
기능
Speed
Logic 설계/analog block 설계
SW 프로그래밍(응용, OS, firmware),
-programming
Cost
만족
회로 설계
Physics
(전자기,
열,전력…)
기본 cell(memory, logic, …) 및 low-level 회로 설계
Signal integrity, radiation/sensitivity, skew, power 소모, yield 해석
검사
4) Another driving force for SoC success ;
Time-to-market
SoC
Bottom line for survival
성능
경쟁력(profit margin)
구현시간(Time-to-Market)
5) SoC success depends on
• Fast implementation
–  IP use, verification methodology
• Team work for
– Job segmentation & reassembly right & rapid mix of
multiple expertise
Name of SoC game(R&D, Education) ;
집중(focus)과 연결(connect)
• 필요한 자질 ;
for individual : 선택과 집중 + communication skill
for group : right intermix of technologies
right intermix of T/NT,
Efficient S&R of task
function/budget/resource
Efficient communication/Cowork
infrastructure
SoC-Specification
• Document-based Specification
– Ambiguous, error-prone
– Specification/implementation gap
• Executable Specification
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–
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–
–
–
Precise behavior description
No communication overhead
Gradual refinement to implementable model
No standard yet
Stable methodology required
CAD tool support required
Specification Language
• HDL-based specification language
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–
–
–
VHDL+, Verilog PLI-2000
Benefit from existing design flow
Relatively slow
Good for hardware description
• HLL-based specification language
– SystemC, SpecC
– Typically based on C/C++
– Good for software/system description
• Mixed form
– Superlog, CoWareC
Why C/C++ based executable
specification language?
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•
•
•
Familiar to the engineering community
General purpose programming language
Mature development environment
Fast execution
SystemC and SpecC offer greatly improved
programming environments
• Increasing availability of tools for the
translation of C to HDL for logic synthesis
• Enables concurrent design of hardware and
software
Required Features
for System Modeling
• Hardware point of view
– Event, timing, concurrency, multi-valued
logic, sequential/combinational logic
• Software point of view
– Dynamic process, recursion, arrays,
structures, I/O libraries, pointers
• System point of view
– Interface, protocol, state machine, queue
Emerging C/C++ Dialects
Language
Company/Organization
Major Feature
A|RT C
Frontier Design
Floating Point Library
CoWareC
CoWare
Co-Simulation with
encapsulated multiple
language
CycleC
CLD
C-to-HDL
CynLib
Forte Design Systems
System Modeling
C-to-HDL
Handel-C
Embedded Solutions
C-to-FPGA
SpecC
STOC
System Modeling
Superlog
Co-Design
Co-Simulation with
one unified language
SystemC
OSCI
System Modeling
SoC Business
– ASIC foundry
– IDM(Independent Device Manufacturer) or
ASSP Provider(Can be fabless)
– IP provider(chipless)
– System Product Manufacturing
– Design Service Providers
– EDA Vendors
Manufacturing
– Silicon foundry offers 0.13 micron digital +
analog, RF, MEMS …
– long IP list desirable
– MPW runs for prototyping
– Reticle generation + fabrication
– P&R, testing, packaging service extra
Manufacturing
– Extremely customized chip may need one
chip/product → faster pipelines in
processing line rather than 12-inch wafer
– Process complexity increase to
cover(memory, ASIC, analog, RF, …)
Testing
– DFT(Design-for-testability) desirable
– Overhead due to test circurity in speed,
area, power  5%
– BIST(Built-in Self Test), Full/Partial Scan
JTAG for board-level testing
– Before/After Packaging/Burn-in
Myths related with SoC
• SoC라는 이름을 일단 쓰면 좋은 일이 생긴다
(건물, 조직, 연구과제, 책, 브로슈어 등)
 실제 내용과 구체적 실행이 정작 중요함
• SoC가 별거냐? 그저 IP의 집합이므로 가져다 모아 쓰기만
하면 된다.
 IP의 개발은 물론, outsourcing 여부 결정과 선택도 어려운 과정임
IP 선정도 개발 경험이 있어야 잘 할 수 있음
• 역시 하드웨어는 HDL로 실계하고 검증해야 한다.
 TTM 단축을 위해 상위 수준 언어(C, C++)가 필요함
• SoC역시 지나가는 fashion일거다. 남들 하는 것 대충 흉
내내고 대강 눈치 껏 하다가, 챙길 것 챙기다 보면 가버릴
것이다. (연구비, 정부혜택,…)
 SoC는 IT(forever)의 핵심 구현 기술이므로, 백년대계로 기술과 인
력 양성까지 준비해야 함
• Moore의 법칙은 결국 깨지고, 기술 발전은 0.07마이크
론 기술에서 중단될 것이다.
 ITRS를 보라. 법칙은 계속 존중되며 준수되고 있다.
• SoC는 대충 남이 만든 IP를 이해하고 가져다 쓸 수 있는
정도의 실력만 있으면 할 수 있다.
자기의 expertise가 확실한 사람만이 타인으로부터 co-work의
후보자가 되듯이, 자기가 만들어 넣은 block이 있어야 빌려온 IP
가 빛난다.
• IP의 가치는 역시 기능과 성능에 있다.
 편리성 (Plug & Play, foundry porting, platform conformity,
documentation, 검증)이 훨씬 더 중요함
SoC Success Story를 위한 대책
• 체계적인 인프라를 구축함 : 기획과 평가
– Roadmap
– Standard(platform, SW I/F, HW block I/F, …)
• 원천적 R&D와 인력 양성에 투자함 (70:30=실용:원
천)
– 대학 :
– 연구소, 기업 :
– 정부 :
• HW와 SW의 mix, 협력에 의한 synergy
• Top-down 설계, 기획
– 사업
– Project
– Chip(high-level설계)
• 기술과 비기술의 concurrence(TTM 단축)
– 경영, 자금, 특허 …
각 나라의 SoC 개발 전략과 현황
• 미국; ITRS, Standard, University,
SIA/Sematech/SRC, Darpa/NSF, MOSIS, VC,
Nasdaq, fabless, Conferences
• 유럽; Big system industries, EC consolidation,
IMEC
• 일본; VDEC/VSAC, Silicon Seabelt, Japan TRS
• 이스라엘; embedded software, encryption
• 대만; example
Taiwan’s Si-Soft Program;
OUTLINE





Motivation
Vision, Mission and Organization of Si-S
oft Program
Development of Human Resources
Development of Advanced Technologies:
National SoC Research Program
Development of Global SoC Design and
Service Park
Brilliant Taiwan IC Design & Foundry
Unit: USD Billion
95
96
97
98
99
00
95 - 01
CAGR
01
Taiwan Fabless
Revenue
0.7
0.8
1.3
1.3
2.2
3.3
3.6
31%
Worldwide
Fabless Revenue
5.9
6.7
7.6
8.7
11.7
16.6
13.9
15%
12%
12%
17%
15%
19%
20%
26%
Taiwan Foundry
Revenue
1.1
1.4
2.0
2.8
4.9
9.0
6.1
33%
Worldwide
Foundry Revenue
5.1
5.0
5.1
5.3
7.5
12.9
8.3
8%
21%
27%
39%
52%
65%
% of share
% of share
70%
73%
Source: Dataquest, FSA, ITRI
Foundry Ranked 1 Worldwide
IC Design Ranked 2 Worldwide, next to USA
Worldwide Top 20 Fabless
Unit:USD Million
2001
Companies
Rank
Nvidia*
1
Qualcomm*
2
Xilinx
3
VIA
4
Broadcom
5
Altera
6
Cirrus Logic
7
MediaTek
8
ATI*
9
SanDisk
10
Qlogic
11
PMC-Sierra
12
Lattice
13
SST
14
ESS
15
16 Globespan Virata
Marvell
17
Realtek
18
Legerity*
19
Sunplus
20
Source: ITIS (2002/03)
2001(e)
2000
1,300
1,180
1,150
1,012
962
839
534
456
465
366
353
323
295
294
271
270
252
216
210
197
735
1,250
1,565
984
1,132
1,376
739
411
711
601
318
694
568
490
303
348
132
194
260
201
01/00
Growth%
76.9%
-5.6%
-26.5%
2.8%
-15.0%
-39.0%
-27.7%
10.9%
-34.6%
-39.1%
11.0%
-53.5%
-48.1%
-40.0%
-10.6%
-22.4%
90.9%
11.3%
-19.2%
-2.0%
00/99
Growth%
96.0%
9.0%
74.0%
183.0%
121.0%
64.0%
39.0%
138.0%
0.0%
143.0%
79.0%
165.0%
76.0%
292.0%
-3.0%
521.0%
--
74.0%
--
56.0%
Country
U.S
U.S
U.S
TW
U.S
U.S
U.S
TW
U.S
U.S
U.S
U.S
U.S
U.S
U.S
U.S
U.S
TW
U.S
TW
Note: *Refer to IC Insights statistics
Visibility of Taiwan Fabless
% of WW Sales
25.9%
Singapore
H K / China
6%
20.7%
19.6%
16%
1999
S Korea
21%
2000
2001(e)
Taiwan in WW Top 10
2
1
2
Taiwan in WW Top 20
3
4
4
Taiwan 57%
Asia Pacific Fabless Nos. in 2000
Source:Dataquest(2001/10)
Note:SiS became an IDM in 2000, not a fabless thereafter
Source:IT IS (2002/03)
Vision
SoC design demands for integrated services.
Customer’s Requirements
Foundry
Mask
Package
Testing
PCB
Assembly
Manufacturing
Service
IP
Collection
Platform
Service
EDA
Service
Data
Center
SoC Design
Services
Design
Based on our own strength in IC manufacturing to develop new ICdesign industry that will benefit the manufacturing sector in return
Participating Government Agencies
Science and Technology Advisory Group (STAG)
Si-Soft Program Coordination and Promotion
National Science Council (NSC)
National SoC Project Coordination
Ministry of Education (MOE)
Human Resources Development
Ministry of Economic Affairs (MOEA)
Division of Industrial Technology
Technology Research Projects
Bureau of Industry
IC Design Park Promotion
Organization of Si-Soft Program
Three Main Components
1. Development of Human Resources
2. Development of Advanced
Technologies
3. Development of Global SoC Design
and Service Park
Development of Human Resources
• Additional 85 faculty members per
year specifically for SoC development
for three years (MOE)
• Establishment of Semiconductor
Design Institute (MOEA)
• SoC graduate research programs (NSC)
Development of
Advanced Technologies
National SoC Research Program
(Budget: US$250M for four years)
Three Areas of Concentration:
Wireless, Optoelectronics and
Embedded Processors
National SoC Research Program
Sub-plan 1
Sub-plan 2
Sub-plan 3
Sub-plan 4
Sub-plan 5
Human
Resource
Innovative
Innovative
Innovative
Product
Platform
IP
Emerging
Industry
Development
Product Verification
2. Innovative
Product
Platform Verification
Leading
Product
Vehicles
+
Foresighted
Matching
Plans
IP Verification
4. Innovative IP
3. Innovative
Platform
Service Verification
5. Emerging Industry
Development
SoC Environment for Global Customers
Silicon IP is the Key
Silicon IP
Product
Specification
Foundry Packaging Testing
Masking
System
Design
IC Design
EDA
Tool
Design Service
Mission of the Design Park
• Strengthen Taiwan Design and Manufacturing Competitivene
ss to Increase the Production Value
• Build Global Image - - - A Place for Semiconductor
• Provide Worldwide Customers with SoC Solution to Enhance
Design Success Rate and Reduce Design Cycle Time
– Develop Broad Ranges of SIPs
-- Online Web Service
– Integrate a Good EDA Platform
– Construct Platform Services
• Encourage Worldwide IP Companies come to Taiwan
• Set a New Business Model
• Cluster Together around Foundry and Backend Services
NCTU, NTHU, …
Development of SoC Design Parks
CIC
Hsinch
u
Nehu
Lung
Yuan
Nankan
g
EDC #II
Nehu
EDC #III
HPCC
IP Mall
Semiconductor
Design Institute
Platform Service
Design Service Net
eLearning Net
NTU, NTSTU, …
Aspire
eLearning
IP
Mall
EDC #I
Aspire
Platform Service
Semiconductor
Manufacturing
Central U..etc.
The Business Model of Global
SoC Design & Service Park
• Target Tenants: New Start-up or Small Compan
ies (under 35 Employees)
• Managed by Incubatioin Center (Private Compa
ny)
• Lower the Entry Barriers of IC Design
• Online Web Service
• Encourage Worldwide IP Companies come to T
aiwan
Lower the Entry Barriers o
f IC Design
•
•
•
•
•
EDA Tool Companies’ On-site Service
Most Advanced Tools
Integrate a Good EDA Platform
Construct Platform Services
EDA Tool’s Charge Based on the Hours
of Use vs. Sunk Cost in the Beginning
Online Web Service
• IP Master on the Web
– Description of IP
– Electrical Characteristics and Timing
– IP Verification and Classification (Gold/Silver/Br
onze)
•
•
•
•
Design Manual/Engineering Information
Data Center and Information Security
Concurrent Design and Remote Debug
Try to Set a New Business Model
Encourage Worldwide IP Companies
to come to Taiwan
• VC (venture capital) Helps Incubate the
New Start-ups
– Investment vs Screening
• IP Mall and Variety of Silicon IPs
• Revenue Increase of Hi-tech Design and
Innovation in Taiwan
e-Collaboration Solution
System Companies
IDMs
IC Design Houses
E
SIP Center

e-Collaboration --- Concurrent
Design Based on Variety of SIPs

Concurrent Design at Different
Time Zones to Shorten Design
Cycle Time

Remote Support and Debug
IC Design Houses
Shorten IC Time to Market

Use SIPs from Taiwan SoC Park


Adapt Taiwan 12” Single Wafer Process


Reduce IC Design/Verification Time 50%
Reduce IC Manufacturing Time
50%
Concurrent Design Environment in Different
Location and Time Zones

Reduce IC Design/Debug/Remanufacturing/Re-testing Time
50%
Future Key Player
Give Me a Lever Long Enough and a Place to Stand,
and I Will Move the Earth
Major
Issues/Challenges of
SoC
SoC 가 가져오는 기회
• 고속 성장하는 consumer product 의 특징은
portable, 저전력 소모, 짧은 TTM (Time-toMarket)임.
• 이외에도 medical/bio/health, smart home,
intelligent building, automotive/vehicle (최신
BMW 에는 processor core 가 1000개 내장됨),
military 시장에서도 SoC 의 엄청난 기능/가격
비, 성능/전력비는 새 응용을 열고 있다.
– 사람의 수명이 길어지고, 출산율은 줄므로 생명과 복
지, 교육 시장이 커 진다.
SoC 가 가져오는 기회
• 메모리와 마이크로프로세서가 견인해 온
반도체공정과 full custom 설계기술보다
SoC 에 의한 시스템설계와 IP 활용기술이
시장을 주도하게 됨.
• Volume 시장을 target 할 수 밖에 없음.
– 0.13 micron 공정의 NRE cost ; $ 1M
– 300 mm wafer 공정은 200 mm 의 1.3 배의
비용으로 2.25 배의 chip 을 얻음.
SoC 가 주는 도전(Overall)
• Market to address; What to design. What are
killer applications to justify volume production?
• How to deal with many different players.
(foundry, EDA vendor, IP vendor, system
house, software/firmware/RTOS vendor,
test/packaging house,…)
• How to reduce the TTM (Time-to-market).
• How to reduce the production cost
SoC 가 주는 도전(process)
• How to integrate various process
technologies (MEMS, analog, DRAM).
• How to handle/model VDSM (Very Deep
Sub-Micron) effect.
• Process uniformity, yield, reliability
• DFM (Design for Manufacturability)
Emerging Design Quality Issues
Spice Modeling
IR Drop
ElectroMigration
Hot Carrier Effect
OPC
VDD
GND
Parasitic RLC
EMI
Coupling Noise
Transmission Line
High Freq. Effect
I/O
Process Variation
Digital
Delay & Power
Analog
Temperature
ESD / Latch-up
Substrate Loss
Substrate Coupling
Board Package
SoC
Reference: H. Yonezawa - ISQED 2000 Tutorial 1.2
New Materials Implications
• Lower dielectric
– Reduce total capacitance
• Copper metalization
– Reduce RC delay
– Avoid electromigration
– Thinner deposition reduces cross coupling
capacitance
• Multi layers of routing
– Relative routing pitch may increase
– Room for shielding
Technical Issues in DSM design
• Manufacturability (chip can’t be built)
–
–
–
–
–
Antenna rules
Density rules
Minimum area rules for stacked vias
CMP(Chemical mechanical polishing) area fill rules
Layout correction for optical proximity effects in
subwavelength lithography, associated verification issue
• Signal Integrity(failure to meet timing targets)
– Crosstalk induced errors
– Timing dependent on crosstalk
– IR drop on power supply
• Reliability ( design failures in the field)
– Electromigraiton on power supply
– Hot electron effect on device
– Wire self heat effect on clock and signals
IR drop
• Voltage drop in supply lines from current
drawn by cells
– Chip malfunctions on certain vectors
– Performance degradation
– Biggest problem : what’s the worst-case vector?
Current depends on driver Type,
Loads, and how often Cell is switched
Voltage depend on currents
of other cells
Power supply network consists of wires of
varying sizes; they must be big enough,
but too big wastes area
Electro-migration
• Power supply lines fail due to excessive current
– Chip eventually fails in the field when wire breaks
• Prevention : wire cross-section to current rules
– Maximum current density for particular materials (via layers)
– Higher limits for short, thin wires due to grain effects
– Copper : 100x resistance to EM  not a problem any more ?
Current depends on driver Type,
Loads, and how often Cell is switched
Voltage depend on currents of other cells
Current limit depends on wire size
Power supply network consists of wires of
varying sizes; they must be big enough,
but too big wastes area
Power IR-drop
DV=I*R
clean VDD
• IR-drop
– Slows down the circuitry
– Inhibits switching and loss of state
– Critical to maintain functionality
and performance
• Increased design complexity
– Smaller TR, longer interconnect
– Long interconnect increases
resistance
– High frequency increases current
density per die size
– IR-drop is more serious than
electro-migration
V
clean GND
Comparison between Previous
Approaches and Proposed Approach
• Previous approaches
– Transistor level analysis at P&R stage
– Long simulation time for exact current estimation in
the full-chip power analysis
– Huge RC netlist for power network
– Large CPU time for iterations
• Proposed approach
–
–
–
–
RTL stage planning method based on floorplan
Reducing turn-around-time
Virtual power grid and current source
Area-based DC current model
Comparison
Early planning
Exact analysis
Switching PAD model
Switching current model
R(L)C network
Transient analysis
Constant drop PAD model
Constant current model
Resistance-only network
DC analysis
current
t
peak current
average current
IO SSN and Power Ground
•
•
•
•
•
Output pad, Bi-direction pad 의 경우 큰 loading 에 따라
large transient current ( di/dt ) 가 흘러 ground bounce 발생.
IO-limited design : Staggered IO, 충분한 power 공급 문제
High Speed - Full swing issue : 외부 칩과의 동작에 대한 모델링 필요.
Inductance Minimizing
VDDIO V33IO
L
R
C
output
input
Package model 388 PBGA
+ bonding wire and lead frame
L = 20nH, R = 0.4 ohm, C = 1.5pF
IO pad
Package
VSSIO
PCB
FR-4 PCB model(7mil)
L = 42 nH, R = 10 ohm, C = 17 pF
Power Ground Planning
VDDIO
VDDcore
VSS
Power/Ground
bouncing
SoC 가 주는 도전(design)
• How to verify the design (functionality).
• How to maintain consistency through
the whole design procedure (EDA tools).
• How to maintain latency insensitiveness
in assembling working IP’s as an SoC.
• DFT (Design for Testability); BIST, scan
chain, JTAG
• DFV (Design for Verifiability)
• Design for Low Power
SoC 는 종래의
ASIC 과 무엇이
다른가?
SoC 는 종래의 ASIC 과
무엇이 다른가?
1. SoC is a black hole (mixture of
heterogeneous technologies)
2. Design Reuse
3. Low Power Design
4. Design/Verification Methodology
5. Embedded Software (up to 80%)
1) SoC 는 블랙홀이다!
•
SoC ; 정보를 표현(입력), 저장, 변환하고 전송 전후 처리를 구현해 주는
mechanism 이다.
•
통신 시스템이 ‘확장되는 Universe’ 라면, SoC 는 System을 빨아들이
는 ’Black Hole’ .
•
SoC 는 주변의 모든 element 들을 빨아 들이면서 계속 강력 농축되어 감.
Digital CMOS 를 기반으로 하는 SoC 는 system integration 의 주력.
2) Design Reuse
• IP reuse is a solution to the productivity gap.
• What is IP?
– IP (Intellectual Property) is composed of
• Design file and document file
• License (copyright, patent, and trade secret)
• Technical support
– Pre-designed and pre-verified macro block
– Other names: VC (Virtual Component), core
IP
SoC
Advantage of Reuse
 Productivity is improved by using the well-designed IP’s.
Design Effort (for a specific function)
 Design for one-time use
 Design by Reuse
= Design Reuse
1st
2nd
3rd
 Design for Reuse
= IP Development
4th
5th
Project (where a specific
function is required.)
Difficulties of IP Reuse
• Standardization of IP deliverables across the
border;
• Marketing problem (눈에 안 보이는 IP를 판다?)
– IP marketing strategy, media, license, pricing policy
• Security problem
– Tradeoff between accessibility and theft protection
• Management problem
– Version control, search, backup and interface
between CAD tools
3) low power, WHY?
1) Battery 기술 발전 slow ! : 5-8배 향상/200yrs
200년전 : 납축전지 25 watt.hour/kg
 now : lithium polymer 전지 : 200 watt.hour/kg
이에 비하면 반도체기술은 30년동안 106배(CPU속도) 매 3년마
다 4배(Memory density)  Still wild wild frontier stretching
before us! (Low power design 은 아직도 풍부한 금맥이다.)
2) 열방출 문제 :
You don’t want big cooling tower for each IC’s !
3) Energy 절약 :
minimize the amount of energy consumption, and
recirculation period, otherwise our earth will be EXHAUSTED.
4) Convenience :
Use battery than too many wires around : mess
Future Opportunities for Low-Power
1) PDA(Personal Digital Assistant) 의 기능;
telephone, pen-based input, schedule keeper,
audio/video entertainment, fax, video camera, data
security with finger,print and/or voice recognition,
speech recognition, appl. S/W, teleconferencing…
Appl.
Server
PDA
Base
Station(RF)
Function sharing
for “low-power”ing PDA
2) Virtual Reality(VR) headset for Games
: allows you to move around, only if there’s no wire.
: delegate complex processing to fixed server, while
performing only video decompression.
3) Military :
No chance for wires, No heavy batteries was your too
busy.
– Information warfare :
1) Soldier locates enemy tank using laser rangefinder with GPS
2) request (for air strike) to control officers
3) aircraft nearby gets command
4) Medical Uses ;
pace maker (implanted), health
monitor, hearing aids, 내시경 로봇,..
5) GPS for traveler, explorer, driver(car, ship, soldiers)
6) RF ID(for identifying people, animal, cars…)
passive type : resonant LC circuits
active type (no battery, draws RF power from RF field)
7) Smart Cards :
주민증, Cash drawing, e-commerce
with encryption, COS (card OS)
4) Design/Verification Methodology
• 왜 Methodology 가 필요한가?
–
–
–
–
Design file version control
Design style 의 통일성(rules, guide)
Disciplined designer (teamwork, reliability)
Experienced project manager (plan,
coordination, trade-off, decision)
– Sufficient tools, stable IP/library/foundry
– Top-down planning/ high-level, early
verification
– Methodology is Infrastructure, not
Overhead.
5) Embedded Software
• 90% of the SoC chip will be
MEMORY.
• 80% of the SoC value will be in
Embedded Software.
한국의 SoC 설계기술
의 발전 전략
SoC in Society, Economy,
Industry, Life and FUTURE!
• IT is the Key technology for the next
50+ years, at least.
• SoC is the ultimate mechanism for
implementing the IT, and is the core of
IT.
• That is why IT is the investment focus
in nearly all advanced/competitive
countries.
IT 산업에서 SoC 의 비중
• IT 산업에서 Embedded System (ES)의
역할과 비중의 증대 ; 현재 약 25%, 향후
5-7 년 후 약 40% 에 접근할 것으로 보임.
• 대부분(95%)의 Embedded System 은
SoC 로 구현될 것임.
• 향후 7 년 후에 우리 나라 경제에서 SoC
가 차지하는 비중은 33% 에 육박할 것으
로 보임.
Fabless House 가 SoC 의 승부처
• SoC 산업의 구성요소는 Foundry, System
House, Fabless House (IP Vendor 포함), EDA
Vendor, IDM (Independent Device
Manufacturer) 임. 현재 시장 규모는 대략
(20;40;10;30) 이나, 향후 7년 후에는
(20;30;30;20) 으로 될 것으로 전망함.
• SoC 산업분야 중에서 가장 빨리 성장하는
Fabless Company 의 경우 World top 20 내에
미국 16, 대만 4개임.(한국도 일본도 전무함)
우리나라의 SoC 경쟁력
• SoC 국가 경쟁력은 1)system 착상/설계
능력, 2)Chip 설계능력, 3)내수시장의 크
기와 국제마케팅능력. 4)chip 제조기술에
대한 종합 score 로 평가해 볼 수 있다.
• 이러한 기준에서 지금 우리나라의 SoC 경
쟁력은 미국, 일본, 대만에 확실히 뒤져 있
고, 캐나다, 프랑스, 독일, 이탈리아, 중국,
영국, 이스라엘 등과 경쟁하는 입장이다.
SoC 에 대한 우리 나라의 입장
• 중국등 경쟁국에 대하여 반도체,TFT LCD,
CDMA 단말기등 일부 산업에서 가지는 경
쟁력차이를 유지/확장하는 유일한 길은
SoC 사업을 활성화하는 길밖에 없음.
– DRAM 산업은 profitability 뿐 아니라, 돈을
번다 해도 번 돈을 거의 모두 계속 차세대 공
장 건설에 투자해야 함.
– TFT LCD 산업은 자본집약적 산업으로 언제
든지 경쟁국에 추월 당할 가능성이 큼.
• System 산업의 경쟁력과 부가가치를 높
이는 길, 역시 시스템 내에 내장되는 SoC
의 가치/비중을 높이는 것임.
SoC 가 우리에게 주는 기회 요인들
• Automobile industry 의 고부가가치화;
– BMW 최신기종에는 processor 가 1000
개!
• Internet, cellular 등 거대한 국내외 통신시
장에서의 지속적인 성장의 기회;
– Qualcomm 은 CDMA 기술 하나로 세계 2
위의 fabless 반도체 (SoC 설계) 회사임.
• Multi-media 단말기, health/defense 시장
한국의 SoC Vision
• Aart de Geus (Synopsys Chairman and
CEO), “한국이 5년후에는 SoC 분야의
world top 6 안에 들게 될 것”
• 실제로 5년후에는 5위. 7년후에는 3위까지
목표로 할 수 있다고 판단됨.
SoC 관점의 한국의 SWOT 분석
• Weakness: 다양성을 다루는데 약함, 즉 분야간/기능간
협력(학제적) 마인드 부족 경청과 협상력 부족(배달민족),
체계적인 개념 정립과 깊은 사고 훈련이 약함. 개인의 능
력과시를 전체 시스템 rule 준수보다 더 중요하게 여김.
영어와 세계시민감각 부족(유아독존). 질보다 양, 내용보
다 형식 우선주의, 근시안적 사고
• Threat: 중국, 인도, 대만, 선진제국과의 경쟁 심화. 이공
계기피심화현상.
• Strength: 도전정신(이길 수 있다). 향학/성취 열정. 자신
감(우리는 해냈다/할 수 있다).
• Opportunity: 반도체, 통신, 자동차 산업의 존재. 내수시
장 있음. 정부의 과학기술 R&D 투자.
어떤 사람을 어떻
게 키울 것이냐?
LESSON #1
• 세 가지 Fundamental 이 강한 사람
이 필요.
– 깊이 생각하는 능력/추진력
– Basic Concept 에 대한 확실한 이해
– 대화/협동 능력
LESSON #2; 연결
• Sector 간, 분야간의 교류와 협력을 위한 infra
를 구축하고 이를 통해 Synergy (TTM, Cost
saving 등) 를 올려야 한다.
– Government and private sector
– Industry and academia
– System industry and IC industry
– hardware designers and software programmers
– System designers and chip designers
– Among IC industries in the pre-competitive stage
1) 개인의 경력/전공 ; 주력분야에서 탁월
하고 인접분야와 연결고리가 있어야!
wireless
전자기
통신
xDSL, switch
MMIC
반도체
회로
VLSI
2) 국가의 경쟁력;교육/연구/business의 연결
교 육
연구/개발
창업/상품화
실력 향상의 효율
동기(motivation)
핵심기술(돌파력)
응용기술(대응능력)
지식 : 고속 단방향 흐름
다자간 쌍방향
3) 기업의 경쟁력; 기술과 비기술의 연결
Top of mountain
특허전략
정상 공격조
경영
투자유치
제휴,M&A
시장심리
지원조
Base Camp
기술표준
.
.
.
SoC = 기회
SOC : System 과 Chip 을 연결함으로
써 생기는 Opportunity
경청하여 주심에 감사드립니다.

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