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Logic and Computer Design Fundamentals Chapter 7 – Registers and Register Transfer Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Propagation Delay: capacitances introduce delay All physical devices have delays due to the charging and discharging of (parasitic capacitors) and interconnection resistance. Crossing lines level tpd t Resistive tube Propagation delay flow 2 Where to these capacitors come from? Most are parasitic caps Cross section of Altera Stratix EP1S25 (TSMC proces Crossing lines passivation Crossing interconnections (Source: IBM) 9 level of interconnections M9 M8 M7 M6 M5 M4 M3 M2 M1 (Source: TSMC) 2um 3 Review: 6-3 Flip-Flop Timing Parameters and metastability Edge triggered flip-flop In C D Q C Q C In (D) tS set-up time th hold time If one violates the set-up time and hold time, the flip-flop can go in a metastable state. 4 Out Metastable behavior Example of metastable behavior: metastable Eventually, the flipflop will settle (Oscilloscope trace) After a while the flip-flop will go into a stable state (randomly). If this happens before the next clock edge, the actual circuits will see a defined input. The longer the clock period is the less chance of synchronization failure. Or use two synchronization flip-flops in series 5 Debouncing PRACTICAL CONSIDERATIONS 6 Practical considerations In many cases the input signals come from push buttons and sensors: • Switches exhibit bouncing • Are not synchronous • Give multiple input (sampled many times) This can give catastrophic failures of timing problems Solutions: • Debounce the switch • Synchronizer • One-pulse circuit (and synchronizer) 7 Bouncing of switches What is bouncing? When closing a switch, the switch contact bounces back and forth, giving multiple pulses 5V Push button switch chip A B Causes spurious glitches on input B Measured signal 8 Debouncing circuit The two resistors will keep S=R=0: • Inputs are never floating • Output does not bounce 5V R R 1 Q S S 2 Push switch contact to 5V Q Q Bouncing No bouncing SR latch Is set S=R=0 No change 9 Likely violation of set up times ISSUES WITH ASYNCHRONOUS INPUTS 10 Asynchronous inputs Asynchronous inputs (e.g. from sensors) can cause timing problems if set up time is violated: tS setup time CLK Signal from sensor This setup time violation can give problems, such as metastability and erroneous operation: stable metastable stable Use a synchronizer 11 Metastability and Synchronization A flip-flop can get into a metastable state: • When the set-up or hold times are violated • This can happen for asynchronous inputs (e.g. push button; sensor input, etc) Input D0i CLK D Sensor asynchronous input Q Q0 Q0 Q1 D1 D Q Both flip flops behave differently! Q1 CLK kick kick Q0 Q0 Q1 12 Metastability (continued) Asynchronous inputs: • Use a synchronizing flip-flop Synchronizer Asynchronous input Di D D0 D Q Q Q0 Q Q1 Ai D1i D • Now, only the synchronizer may get into the metastable state; however, there is a good chance that by the end of the clock period it went into one of the stable states. 13 Synchronizer Sensor,async Di D Q Ai Synchronized output CLK CLK Signal from sensor Synchronized output Note: by having the sensor input enter through a single D flip-flop the problem of timing circuits is reduced greatly (there is still a small chance that the D FF will be unstable). By using two D flip-flops in series one further reduces the risk that the 2 nd FF will be metastable. 14 Chapter 7 Registers and Register Transfers (Source: reference.findtarget.com) 15 7-1 Registers Register – a collection of flip-flops, together with some combinational logic, that performs data processing tasks (e.g. storing, moving data, etc). In theory, a register is sequential logic which can be defined by a state table. More often think of a register as storing a vector of binary values. 16 Simple Storage Register inputs Outputs • A D flip-flop register loads information on every clock cycle! • To “store” or “load” information should be controlled by a signal. Active low Clear (asynch) 17 Register with Parallel Load: Clock Gating Use a signal to block the clock to the register Load is a frequent name for the signal that controls register storage and loading • Load = 1: Load the values on the data inputs • Load = 0: Store the values in the register Clock gating: 1 Timing: Gated clock: To C input of Flip-flops Clock Load Gated Clock to FF Extra edge! 18 Registers with Load-Controlled Feedback A more reliable way to selectively load a register: • Run the clock continuously, and • Selectively use a load control to change the register contents. 2-to-1 Multiplexers Example: 2-bit register with Load Control: For Load = 0, A1 loads register contents Y1 D Q (hold current values) Load In1 For Load = 1, C loads input values (load new values) A0 Y0 Hardware more complex D Q C than clock gating, but free of timing problems In0 Clock 19 Registers with Load Control: Example K1=1: R1 stores the result of addition/subtraction 20 7-2 Register Transfers The data is stored in registers, which compose the datapath. (Source: reference.findtarget.com) In many cases one wants to perform a variety of arithmetic and logical operations on a set of data bits (e.g. a 16-bit word): • Additions, subtraction, shifting, loading, etc. 21 Register Transfers Operations The type of operations on the data will be determined by a controller, often called a control unit. (Source: reference.findtarget.com) This division between the datapath and control unit makes the design of complex systems easier. Strategy: divide and conquer! Registers play a key role in complex digital systems! 22 Datapath and Control Unit Control signals Control Unit Status signals Determines which operation and sequence of operation based on status signals Control signals: activate various operations in the datapath Is a large finite state machine Datapath Stores data in registers Performs operations on data, specified by Cntr unit Provide status signals Is defined by registers and its operations: Register Transfer Operations (RTL) An elementary operation: microoperation 23 7-3 Register Transfer Operations Register Transfer Operations – The movement and processing of data stored in registers Three basic components: • set of registers • operations • control of operations Elementary Operations -- load, count, shift, add, bitwise "OR", etc. • Elementary operations called microoperations Register Notation: Ex. 8-bit register R: 16-bit registers: MSB 7 …1 0 LSB R 15 8 7 0 PC(H) PC(L) 15 0 R2 24 Conditional Transfer If (K1 =1) then (R2 R1) is shortened to K1: (R2 R1) where K1 is a control variable specifying a conditional execution of the microoperation. K1 R1 n Load R2 Clock Clock Clock K1 K1 Transfer occurs here No Transfers Occur Here Transfer occurs here No Transfers Occur Here 25 7-5 Microoperations Logical Groupings: • Transfer - move data from one set of registers to another • Arithmetic - perform arithmetic on data in registers • Logic - manipulate data or use bitwise logical operations • Shift - shift data in registers Arithmetic operations + Addition – Subtraction * Multiplication / Division Logical operations (bitwise) Logical OR Logical AND Logical Exclusive OR Not 26 Example Microoperations Add the content of R1 to the content of R2 and place the result in R1. R1 R1 + R2 Multiply the content of R1 by the content of R6 and place the result in PC. PC R1 * R6 Exclusive OR the content of R1 with the content of R2 and place the result in R1. R1 R1 R2 27 Example Microoperations (Continued) On condition K1 OR K2, the content of R1 is Logic bitwise ORed with the content of R3 and the result placed in R1: • (K1 + K2): R1 R1 R3 NOTE: "+" (as in K1 + K2) and means “OR.” In R1 R1 + R3, + means “plus.” 28 Arithmetic Microoperations Symbolic Designation R0 R1 + R2 R0 R1 R0 R1 + 1 R0 R2 + R1 + 1 R1 R1 + 1 R1 R1 – 1 Description Addition Ones Complement Two's Complement R2 minus R1 (2's Comp) Increment (count up) Decrement (count down) Note that any register may be specified for source 1, source 2, or destination. These simple microoperations operate on the whole word 29 Implementation of an Arithmetic Micro operation Conditional microoperation: X K1 : R1 R1 + R2 X K1 : R1 R1 + R2 + 1 Condition 30 Logical Microoperations Symbolic Designation R0 R1 R0 R1 R2 R0 R1 R2 R0 R1 R2 Description Bitwise NOT Bitwise OR (sets bits) Bitwise AND (clears bits) Bitwise EXOR (complements bits) 31 Logical Microoperations (continued) Let R1 = 10101010, and R2 = 11110000 Then after the operation, R0 becomes: R0 01010101 Operation R0 R1 11111010 R0 R1 R2 (sets bits) 10100000 R0 R1 R2 (clears bits) 01011010 R0 R1 R2 (complements bits) 32 Shift Microoperations Symbolic Designation Let R2 = 11001001 R1 sl R2 Then after the operation, R1 R1 sr R2 becomes: R1 10010010 01100100 Description Shift Left Shift Right Operation R1 sl R2 R1 sr R2 Note: These shifts "zero fill". Sometimes a separate flip-flop is used to provide the data shifted in, or to “catch” the data shifted out. Other shifts are possible (rotates, arithmetic). 33 7-6: Microoperation on a Single Register Microoperation on a Single Register • • • • • MUX-based transfers Shift registers (needed for Lab) Ripple Counter Synchronous binary counter Other counters 34 7-6 Microoperations on a Single Register The focus is on the implementation of microperations with a SINGLE register as the Destination of the results In addition to the register there is some combinational logic needed. This is considered part of the register and is called DEDICATED logic (in contrast to SHARED logic for multiple destination registers). Multiplexer-based transfer: makes use of multiplexers to allow multiple operations on a single destination register (See next) 35 Multiplexer-Based Transfers Multiplexers connected to register inputs produce flexible transfer structures Consider the following Load circuit K R2 K1 n n Load R1 2 Load S 0 MUX 1 n R0 Combinational circuit What are the corresponding Register Transfer operations of the following implementation? 36 Register Transfer Operations implemented by the following circuit • K1.K2: R0 R1 • K1.K2: R0 R2 Load R2 K1 n n Load K2 Load S 0 MUX 1 n R0 R1 37 Exercise Consider the following circuit (Note: Clocks are omitted for clarity) Load R2 K2 K1 S n 0 n Load MUX 1 Load n R0 R1 What are the corresponding Register Transfer operations? 38 Shift Registers Shift Registers move data laterally within the register toward its MSB or LSB position In the simplest case, the shift register is simply a set of D flip-flops connected in a row like this: B A In DQ DQ C DQ Out DQ CP Data input, In, is called a serial input or the shift right input. Data output, Out, is often called the serial output. The vector (A, B, C, Out) is called the parallel output. 39 Shift Registers (continued) The behavior of the In serial shift register is given in the listing on the lower right T0 is the register Clock CP state just before Clock the first clock pulse occurs T0 T1 is after the T1 first pulse and T2 before the second. T3 Initially unknown T4 states are denoted by “?” T5 T6 Complete the last three rows of the table B A DQ In 0 1 1 0 1 1 DQ A ? 0 1 1 C DQ B ? ? 0 1 Out DQ C ? ? ? 0 Out ? ? ? ? 1 40 Shift Registers (continued) B A In DQ DQ C DQ Out DQ Clock CP CP T0 T1 T2 T3 T4 T5 In 0 1 1 0 1 1 T6 1 A ? 0 1 1 B ? ? 0 1 C ? ? ? 0 Out ? ? ? ? 0 1 1 1 0 1 1 1 0 0 1 1 41 Parallel Load Shift Registers MUX By adding a mux DA between each shift register A stage, data can be D shifted or loaded IN Q If SHIFT is low, A and B are SHIFT replaced by the data on DA CP and DB lines, else data shifts right on each clock. By adding more bits, we can make n-bit parallel load shift registers. SHIFT: Q sr Q SHIFT’: Q D Register Transfer Operation: DB B D Q 42 Parallel Load Shift Registers with Load Serial input D0 2 1 0 D Q S1 S0 Shift Load D1 Control Shift Load D2 D0 C D Q S1 S0 Use a multiplexer with 3 inputs: Serial input 2 1 0 2 1 0 S1 S0 = 2 1 0 Q1 C D S1 S0 Shift Load Q0 Q Q2 C Shift Load 43 Timing Clock Load (Shift = 0) Di Qi Output changes here Register Transfer Operation: Shift: Q sl Q Shift.Load: Q D 44 Bidirectional shift register 45 Counters Counters are sequential circuits which "count" through a specific state sequence. They can count up, count down, or count through other fixed sequences. Two distinct types are in common usage: Ripple Counters • Clock is connected to the flip-flop clock input on the LSB bit flip-flop • For all other bits, a flip-flop output is connected to the clock input, thus circuit is not truly synchronous • Output change is delayed more for each bit toward the MSB. • Resurgent because of low power consumption Synchronous Counters • Clock is directly connected to the flip-flop clock inputs • Logic is used to implement the desired state sequencing 46 Ripple Counter How does it work? • When there is a positive Clock edge on the clock input of A, A complements • The clock input for flipflop B is the complemented output of flip-flop A Reset • When flip A changes from 1 to 0, there is a positive edge on the CP clock input of B A causing B to complement B 0 1 A D CR D B CR 2 3 0 1 47 Ripple Counter (continued) The arrows show the cause-effect relationship from the prior slide => The corresponding sequence of states => CP A B 0 1 2 3 0 1 (B,A) = (0,0),(0,1), (1,0), (1,1), (0,0), (0,1), … Each additional bit, C, D, …behaves like bit B, changing half as frequently as the bit before it. For 3 bits: (C,B,A) = (0,0,0), (0,0,1), (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), (1,1,1), (0,0,0), … 48 Delays in a Ripple Counter Starting with C = B = A = 1, the next clock increments the count to (C,B,A) = 0; thus from (111) to (000) In fine timing detail: The clock to output delay tPHL causes an increasing delay from clock edge for tPHL each stage transition. CP • Thus, the count “ripples” from least to most A 1 significant bit. • For n bits, total worst case B 1 delay is n tPHL. C 1 tPHL 0 0 0 tpHL 1 0 0 1 1 0 49 Ripple Counter (continued) These circuits are called ripple counters because the changes “ripple” through the chain of flip-flops, i. e., each transition occurs after a clock-to-output delay from the stage before. Disadvantages: • Slow operation due to the delays • Intermediate results with can give rise to unreliable operation in digital circuits Advantages: • Simple hardware • Low power consumption 50 Synchronous Counters To eliminate the "ripple" effects, use a common clock for each flip-flop and a combinational circuit to generate the next state. For an up-counter, use an incrementer => Comb. Logic Incrementer A3 S3 D3 Q3 A2 S2 D2 Q2 A1 S1 D1 Q1 A0 S0 D0 Q0 Clock 51 Synchronous counter Clock Q0 1 1 1 Q1 1 1 Q2 Q0: changes at every clock EN D Q Q0 When EN=1: XOR inverts and Q0=D’ C Q0 Q1: changes when Q0 = 1: D EN Q1 C Q1 Q2: changes when Q0 and Q1 = 1 Q D Q Q2 C 52 Synchronous counter – parallel gating Incrementer •Replace AND carry chain with ANDs => in parallel •Advantages •Reduces path delays •Called parallel gating •Like carry lookahead Symbol: Carry Out CO 53 Synchronous Counter with an Arbitrary Sequence Start with the state diagram or the state table Decide which flipflops to use Find the combinational logic (inputs to the flipflops) Draw or build the circuit 000 110 001 101 010 100 54 Design Exercise: Arbitrary Sequence 000 110 001 101 010 100 55 Arbitrary Count sequence: next state equation 3 Flip-flops required Find the next state equations: DC, DB, DA. DA Be careful with Table sequence DB DA = A’B+AB’ = AB DC = B’C’ DB = C A B 0 1 x 0 0 1 x 0 C A B 0 0 x 1 1 1 x 0 C DC A B 1 0 x 0 1 0 x 0 C 56 Counter schematic DA = A’B+AB’ = AB DB = C DC = B’C’ What about unused states? Complete the state diagram 57