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Report
Registers & Counters
Mantıksal Tasarım – BBM231
M. Önder Efe
[email protected]
1
Registers
• Registers are clocked sequential circuits
• A register is a group of flip-flops
– Each flip-flop capable of storing one bit of information
– An n-bit register
• consists of n flip-flops
• capable of storing n bits of information
– besides flip-flops, a register usually contains
combinational logic to perform some simple tasks
– In summary
• flip-flops to hold information
• combinational logic to control the state transition
2
Counters
• A counter is essentially a register that goes through a
predetermined sequence of states
• “Counting sequence”
FF0
FF1
Register
FFn-1
Combinational logic
3
Uses of Registers and Counters
• Registers are useful for storing and manipulating
information
– internal registers in microprocessors to manipulate data
• Counters are extensively used in control logic
– PC (program counter) in microprocessors
4
4-bit Register
D0
Q
D
Q0
REG
C
R
clear
D1
Q
D
Q1
C
R
D2
Q
D
D0
Q0
D1
Q1
D2
Q2
D3
Q3
Q2
C
FD16CE
R
D3
Q
D
C
clock
clear
5
16
R
Q3
D[15:0]
Q[15:0]
CE
C
CLR
16
Verilog Code of FD16CE
always @ (posedge C or posedge CLR)
begin
if (CLR)
Q <= 4’b0000;
else
begin
if (CE)
Q <= D;
end
end
Register with Parallel Load
Load
D
D0
Q
Q1
Q
Q2
Q
Q3
R
D1
C
R
D
D2
C
R
D
clock
7
clear
Q0
C
D
D3
Q
C
R
Register Transfer 1/2
load
n
R1
R2
R2  R1
clock
clock
R1
010…10
110…11
load
8
R2
010…10
Register Transfer 2/2
n-bit
adder
n
n
load
R1
clock
R1  R1 + R2
9
R2
Shift Registers
• A register capable of shifting its content in one or
both directions
– Flip-flops in cascade
serial
input
SI
Q
D
C
Q
D
C
Q
D
C
Q
D
SO
C
clock
•
The current of n-bit shift register state can be transferred in n clock cycles
10
serial
output
Serial Mode
• A digital system is said to operate in serial mode
when information is transferred and manipulated
one bit a time.
SI
shift register A
clock
SO
SI
shift register B
clk
clk
shift
control
clock
shift
control
clk
11
T1
T2
T3
T4
SO
Serial Transfer
BA
• Suppose we have two 4-bit shift registers
Timing pulse
Shift register A
Shift register B
initial value
1
0
1
1
0
0
1
0
1
0
1
1
1
0
1
1
After T1
After T2
After T3
After T4
clock
clk
shift
control
clk
12
B
A
T1
T2
T3
T4
shift
control
clock
clk
Serial Addition
• In digital computers, operations are usually executed
in parallel, since it is faster
• Serial mode is sometimes preferred since it requires
less equipment
serial
output
SI
clock
shift
control
serial
input
SO
shift register A
a
b
S
FA
C_in
SI
SO
shift register B
Q
D
C
13
clear
C
Example: Serial Addition
• A and B are 2-bit shift registers
clock
shift
control
01
00
10
01
00
00
SR-A
SR-B
C_in
14
Universal Shift Register
• Capabilities:
1.
2.
3.
4.
5.
6.
15
A “clear” control to set the register to 0.
A “clock” input
A “shift-right” control
A “shift-left” control
n input lines & a “parallel-load” control
n parallel output lines
4-Bit Universal Shift Register
parallel outputs
C
A3
A2
A1
A0
Q
Q
Q
Q
D
C
D
C
D
C
D
clear
clk
s1
41
MUX
3 2 1 0
s0
41
MUX
3 2 1 0
41
MUX
3 2 1 0
serial
input for
shift-left
serial
input for
shift-right
16
41
MUX
3 2 1 0
parallel inputs
Verilog Code – v1
// Behavioral description of a 4-bit universal shift register
// Fig. 6.7 and Table 6.3
module Shift_Register_4_beh (
// V2001, 2005
output reg [3: 0] A_par,
// Register output
input [3: 0] I_par,
// Parallel input
input s1, s0,
// Select inputs
MSB_in, LSB_in,
// Serial inputs
CLK, Clear_b
// Clock and Clear
always @ ( posedge CLK, negedge Clear_b) // V2001, 2005
if (Clear_b == 0) A_par <= 4’b0000;
else
case ({s1, s0})
2'b00: A_par <= A_par;
// No change
2'b01: A_par <= {MSB_in, A_par[3: 1]};
// Shift right
2'b10: A_par <= {A_par[2: 0], LSB_in};
// Shift left
2'b11: A_par <= I_par;
// Parallel load of input
endcase
endmodule
17
Verilog Code – v2
// Behavioral description of a 4-bit universal shift register
// Fig. 6.7 and Table 6.3
module Shift_Register_4_beh (
// V2001, 2005
output reg [3: 0] A_par,
// Register output
input [3: 0] I_par,
// Parallel input
input s1, s0,
// Select inputs
MSB_in, LSB_in,
// Serial inputs
CLK, Clear_b
// Clock and Clear
always @ ( posedge CLK, negedge Clear_b) // V2001, 2005
if (Clear_b == 0) A_par <= 4’b0000;
else
case ({s1, s0})
// 2'b00: A_par <= A_par; // No change
2'b01: A_par <= {MSB_in, A_par [3: 1]}; // Shift right
2'b10: A_par <= {A_par [2: 0], LSB_in}; // Shift left
2'b11: A_par <= I_par; // Parallel load of input
endcase
endmodule
18
Universal Shift Register
Mode Control
19
s1
s0
Register operation
0
0
No change
0
1
Shift right
1
0
Shift left
1
1
Parallel load
Counters
• registers that go through a prescribed sequence
of states upon the application of input pulses
– input pulses are usually clock pulses
• Example: n-bit binary counter
– count in binary from 0 to 2n-1
• Classification
1. Synchronous counters
•
flip-flops receive the same common clock as the pulse
2. Ripple counters
•
20
flip-flop output transition serves as the pulse to trigger
other flip-flops
Binary Ripple Counter
3-bit binary ripple counter
21
0
0 0 0
1
0 0 1
2
0 1 0
3
0 1 1
4
1 0 0
5
1 0 1
6
1 1 0
7
1 1 1
0
0 0 0
• Idea:
– to connect the output of one flip-flop to
the C input of the next high-order flipflop
• We need “complementing” flip-flops
– We can use T flip-flops to obtain
complementing flip-flops or
– JK flip-flops with its inputs are tied
together or
– D flip-flops with complement output
connected to the D input.
4-bit Binary Ripple Counter
Q
T
count
A0
C
R
Q
T
A1
C
R
Q
T
A2
C
R
logic-1
Q
T
C
R
clear
22
A3
0
0 0 0 0
1
0 0 0 1
2
0 0 1 0
3
0 0 1 1
4
0 1 0 0
5
0 1 0 1
6
0 1 1 0
7
0 1 1 1
8
1 0 0 0
9
1 0 0 1
10
1 0 1 0
11
1 0 1 1
12
1 1 0 0
13
1 1 0 1
14
1 1 1 0
15
1 1 1 1
0
0 0 0 0
count
D
Q
A0
Q
A1
Q
A2
Q
A3
C
R
D
C
R
D
C
R
D
C
R
clear
4-bit Binary Ripple Counter
T
count
Q
A0
Q
A1
Q
A2
Q
A3
C
R
T
C
R
T
C
R
logic-1
T
C
R
clear
23
Synchronous Counters
• There is a common clock
– that triggers all flip-flops simultaneously
– If T = 0 or J = K = 0 the flip-flop
does not change state.
– If T = 1 or J = K = 1 the flip-flop
does change state.
• Design procedure is so simple
– no need for going through sequential
logic design process
– A0 is always complemented
– A1 is complemented when A0 = 1
– A2 is complemented when A0 = 1 and A1 = 1
– so on
24
0
0 0 0
1
0 0 1
2
0 1 0
3
0 1 1
4
1 0 0
5
1 0 1
6
1 1 0
7
1 1 1
0
0 0 0
4-bit Binary Synchronous Counter
J
Count_enable
Q
A0
Q
A1
Q
A2
Q
A3
C
K
J
C
K
J
Polarity of the
clock is not
essential
C
K
J
C
K
25
clock
to next
stage
Timing of Synchronous Counters
clock
A0
A1
A2
A3
26
Timing of Ripple Counters
clock
A0
A1
A2
A3
27
27
Up-Down Binary Counter
• When counting downward
– the least significant bit is always
complemented (with each clock
pulse)
– A bit in any other position is
complemented if all lower
significant bits are equal to 0.
– For example:
0 1 0 0
• Next state:
– For example:
• Next state:
28
1 1 0 0
0
0 0 0
7
1 1 1
6
1 1 0
5
1 0 1
4
1 0 0
3
0 1 1
2
0 1 0
1
0 0 1
0
0 0 0
Up-Down Binary Counter
up
T
down
Q
A0
Q
A1
Q
A2
C
T
C
T
C
• The circuit
29
clock
C
Binary Counter with Parallel Load
count
load
D0
J
Q
A0
Q
A1
Q
A2
C
K
D1
J
C
K
D2
J
C
K
clock
clear
30
carry
output
Binary Counter with Parallel Load
Function Table
31
clear
clock
load
Count
Function
0
X
X
X
clear to 0
1

1
X
load inputs
1

0
1
count up
1

0
0
no change
• Ring Counter
Other Counters
– A ring counter is a circular shift register with only one
flip-flop being set at any particular time, all others are
cleared.
shift
right
initial value
1000
T0
T1
T2
T3
• Usage
– Timing signals control the sequence of operations in a digital system
32
Ring Counter
• Sequence of timing signals
clock
T0
T1
T2
T3
33
Ring Counter
• To generate 2n timing signals,
– we need a shift register with ? flip-flops
• or, we can construct the ring counter with a binary
counter and a decoder
T0
T1
T2
2x4
decoder
count
34
2-bit counter
T3
Cost:
• 2 flip-flops
• 2-to-4 line decoder
Cost in general case:
• n flip-flops
• n-to-2n line decoder
• 2n n-input AND gates
• n NOT gates
Johnson Counter
• A k-bit ring counter can generate k
distinguishable states
• The number of states can be doubled if the shift
register is connected as a switch-tail ring counter
Q
D
X
X’
35
Y
C
C
clock
Q
D
Q
D
Z
T
C
C
Y’
Q
D
Z’
T’
Johnson Counter
• Count sequence and required decoding
sequence number
Flip-flop outputs
Output
X
Y
Z
T
1
0
0
0
0
S0 = X’T’
2
1
0
0
0
S1 = XY’
3
1
1
0
0
S2 = YZ’
4
1
1
1
0
S3 = ZT’
1
1
1
1
S4 = XT
0
1
1
1
S5 = X’Y
7
0
0
1
1
S6 = Y’Z
8
0
0
0
1
S7 = Z’T
5
6
36
Johnson Counter
• Decoding circuit
S0
S1
S2
Q
D
C
clock
37
X
S3
S4
Q
D
C
Y
S5
Q
D
C
Z
S6
S7
Q
D
C
T
Unused States in Counters
• 4-bit Johnson counter
0000
1000
0001
0011
38
0111
1100
0010
1110
0101
1111
1011
1001
0100
1010
0110
1101
Correction
0000
1000
0001
0011
39
0111
1100
0010
1110
0101
1111
1011
1001
0100
1010
0110
1101
Johnson Counter
Present State
40
Next State
X
Y
Z
T
X
Y
Z
T
0
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
1
1
0
0
1
0
0
0
0
0
1
0
0
1
0
1
0
1
0
1
0
1
1
0
1
1
1
0
1
0
1
1
0
0
1
1
0
1
0
1
1
1
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
K-Maps
ZT
ZT
XY
00
01
11
10
XY
01
11
10
00
1
1
00
01
1
1
01
11
1
1
11
1
1
1
1
10
1
1
10
1
0
1
1
Y(t+1) = XY + XZ + XT’
X(t+1) = T’
ZT
XY
ZT
00
01
11
10
00
XY
00
01
11
10
00
1
1
01
1
1
1
1
01
1
1
11
1
1
1
1
11
1
1
10
1
1
10
41
00
Z(t+1) = Y
T(t+1) = Z
Unused States in Counters
• Remedy
X(t+1) = T’
Z(t+1) = Y
Y(t+1) = XY + XZ + XT’
T(t+1) = Z
DY = X(Y+Z+T’)
Q
D
C
clock
42
X
Q
D
C
Y
Q
D
C
Z
Q
D
C
T

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