2009 Emerging Logic Devices

Report
2009 Emerging Logic Devices
ERD Working group
George Bourianoff
June 25, 2009
Status
Technology Entry
CNT FETS
Graphene NR FETs
Naonwire FETs
III-V FETs
Ge FETs
Unconventional Geormetries
Novel S-D architectures
Reporter
Mike Garner
Jeff Petterson
Shamik Das
Ken Uchida, Japan ERD
Ken Uchida, Japan ERD
Japan ERD
Simon Deleonibus
Table 1
Reporter status
agreed
agreed
agreed
agreed
agreed
agreed
agreed
Tunnel FET
Adrian Ionescu
I - MOS
Simon Delionibus
Spin FET (Sugahara and Tanaka)Prof Sugahara
SET (Including molecular SRT) Prof Fujiwara
NEMS
Alan Seabaugh
Negative Cg FET
Adrian Ionescu
Table 2
agreed
agreed
agreed
agreed
agreed
agreed
Collective spin devices (spin waveBourianoff
and ferromagnetic)
Moving Domain Wall
Nikonov
Atomic Switch
Hasagara
Molecular Devices
Rainer Wasser ?
Pseusdospinteronic
Sanjay Banarjee
MQCAs
Jeff Bokor?
Table 3
agreed
agreed
agreed
agreed
agreed
agreed
Delivered
Text - need params
follow up sent
follow up sent
all params = CMOS
Test -need params
Text -need params
Text -need params
Email
garner, mike
peterson, jeff
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
re promised
sent reminder
Text - need params
nikonov, dmitri
[email protected]
[email protected]
[email protected]
CNT FETs
Device
• Prepared by Mike
Garner
• HF characterization
and operation –
measured ft of 4 GHz,
projected ft of 6.3 THz
• Circuit speeds much
lower (220 Hz?)
Typcal example devices
Cell Size
Demonstrated
(spatial pitch)
Density
2
(device/cm )
Projected
FET Extension
FET [A] 1D structures
Channel
replacement
Si CMOS
CNT FET III-V compound
semiconductor
channel
replacement
100 nm
100 nm [C]
15 nm
590 nm
~1.5 m [D]
28 nm
Projected
Demonstrated
Projected
Demonstrated
Projected
Demonstrated
1E10
2.8E8
12 THz
1 THz
61 GHz
5.6 GHz
4.5E9
4E7
6.3 THz [E]
4GHz [X1]
61 GHz [C]
220 Hz [G]
5.0E10
4.0E7
>1 THz
>500 GHz
200 GHz
100 GHz
Projected
3E-18
3E-18
3.00E-18
Demonstrated
1E-16
1E-11 [G]
5.00E-15
Projected
238
238 [C]
1.00E4
Demonstrated
1.6
1E-8
4.00E0
Operational Temperature
RT
RT
Materials System
Si
RT
CNT,
Switch Speed
Circuit Speed
Switching
Energy, J
Binary
Throughput,
2
GBit/ns/cm
Research activity[A]
171
InGaAs, InAs,
InSb
Nanowire FETs
• Prepared by Shamik Das
• Expanded set of
materials
– (GaN, AlN, InN, GaP, InP,
GaAs, InAs), II-VI materials
(CdSe, ZnSe, CdS, ZnS),
as well as semiconducting
oxides (In2O3, ZnO, TiO2),
etc
• Additional fabrication
methods - VLS
• No additional circuit
verifications since 2005??
Device
Typical example devices
Cell Size
Projected
Demonstrated
Demonstrated
(spatial pitch)
Density
2
(device/cm )
Switch Speed
Circuit Speed
FET [B]
Si CMOS
FET Extension
1D structures
NW FET
100 nm
30 nm
590 nm
1 m [C]
Projected
Demonstrated
Projected
Demonstrated
Projected
Demonstrated
1E10
2.8E8
12 THz
1 THz
61 GHz
5.6 GHz
1E11
1E8
6.5 THz [D]
250 GHz [E]
100 GHz [F]
11.7 MHz [G]
Projected
3E-18
4E-20 [H]
Demonstrated
1E-16
2.6E-16 [I]
Projected
610
1E4
Demonstrated
1.6
1.2E-3
Operational Temperature
RT
Materials System
Si
RT
Si, Ge, III-V, II-VI,
In2O3, ZnO, TiO2, SiC
Switching
Energy, J
Binary
Throughput,
2
GBit/ns/cm
Research Activity [A]
447
Update to SET entry
• Update prepared by Dr. Akira Fujiwara, NTT
labs
• Principle change is in “demonstrated Switch
speed”
– In 2007, value was 2 GHz obtained from capacitance
measurements
– In 2009, value of 2 GHz is retained but was obtained
from direct RF measurements and reference is
provided
– In addition, some references were updated
• Not a tremendous amount of activity
• Should we move this to transition table in 2011?
Atomic Switch
• Prepared by T
Hasegawa
• Switching times of
20 MHz and 1011
repetitions
demonstrated for 2
terminal device
• challenges are
understanding
device physics,
nonvolatile device
physics
Table entries
•This is a table 3 entry
•Many of the
parameters for a table
2 entry are known
•Should we create a
column in both Table 2
and 3?
Atomic Switch table entries
Parameters for table 1
Cell size: 10 nm (projected), 20 nm (demonstrated)
These are in the case of two-terminal atomic switch.
For three-terminal, 6F2 is required including electrodes.
For three-terminal, demonstrated size is 3m x 3m.
Density (devices/cm2): 2x1011(Projected), 2x109(demonstrated),
Switch speed: > 1GHz (Projected), 10 MHz (demonstrated)
Circuit Speed: Not known
Switching Energy (J): 1E-18 (Projected), 1E-10 (demonstrated)
Binary Throughput: Not known
Operational Temperature: RT
Materials System: metal oxides, sulfides,
Research activity:
For table 3
State variable: metal cations / atoms
Response function: Non-linear
Class example: programmable logic
Architecture: crossbar, morphic
Application: elements in nonvolatile logic
Pros: Low on-resistance, low power consumption, nonvolatility
Status: demo.
MEMS switch
• Section prepared by
Alan Seabaugh, ND
• Low static power
dissipation
• Challenges is low
voltage (1 V) at GHz
frequencies
• Reliability, repeatably
and burn out
• Table entries
• This is a table 3 entry
• Many of the
parameters for a table
2 entry are known
• Should we create a
column in both Table
2 and 3?
MEMS Switch table entries
•
Entries and References for Logic Table [2]
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
NEM Switches
NEMFET
Cell Size Projected
100
nm
Cell Size Demonstrated
900
nm
Density Projected
1E10
devices/cm2
Density Demonstrated
1
devices/cm2
Switch Speed Projected
1
GHz
Switch Speed Demonstrated
<0.18
Circuit Speed Projected 1
GHz
Circuit Speed Demonstrated
<0.18
Switching Energy Projected
5E-17
Switching Energy Demonstrated
Binary Throughput Projected
10
Binary Throughput Demonstrated
Operational Temperature RT
Materials System: Al, polySi, TiN, CNT
Research Activity (2008-2009)
20
•
Entries for logic Table 3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
NEM Swtich
State variable
charge
Response function
mechanical position
Class example
NEMFET
Architecture
von Neumann
Application
logic
Constraints
mechanical
Pros
<60 mV/dec
low static power
complementary
CMOS compatibility
radiation tolerant
Cons
delay > 1 ns
VT >1
wear. stiction
bounce
Status
demo
Material issues
sticktion,
contact wear
[3]
[2]
[4]
GHz
GHz
J
J
Gbit/ns/cm2
Gbit/ns/cm2
[5]
[6,7]
NEM switch publications
Pseudospin devices
• Excitonic electron hole
Bose Einstein
Condensates
• Above room temperature
Bi-layer graphene
systems theoretically
predicted
• Graphene because of AB
stacking, valence –
conduction band
symmetry, low density of
states, low defencts, …
• Electron transport
controled by gate bias
• Table 3 entry
• Ultra low power ~10-20
J/op
• Reasonably fast
~100GHz
• Room Temp operation
• Non CMOS like I/V
characteristics > non
CMOS like circuits
BISFET table entries
State variable
Response function
Class example
Architecture
Application
e.g, which “layer” degree of freedom in graphene bi-layer
e.g., gate controlled negative differential resistance
Bilayer Psuedospin Field Effect Transitor (BiSFET)
Non-classical “post” CMOS
General purpose logic
Constraints
Pros
Cons
Status
Material issues
extremely low power
requires novel clocking scheme
theory and simulation only; early stages
Intrinsically graphene bi-layers for BiSFET
Ferromagnetic logic and MQCAs
• Minor updates from previous version
– Creation of biaxial anisotropy
– Current driven moving domain wall gates
– New results on power dissipation in
nanomagnetic circuits (ripple adder) relative
to CMOS
Summary
• Chapter had contained 19 entries in 3
tables
• 4 contributors have not sent anything
• 5 contributors sent text but are missing
table entries
• 8 entries are
• 1 will not be done – novel S/D
architectures

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