Slide 1

Report
Fast Waveform Digitizing in Radiation Detection
using Switched Capacitor Arrays
Stefan Ritt
Paul Scherrer Institute, Switzerland
Question ?
4 channels
5 GSPS
1 GHz BW
8 bit (6-7)
15k$
Sept 25th, 2009
4 channels
5 GSPS
1 GHz BW
11.5 bits
1k$
USB Power
CMOS ET Vancouver
2
The need for speed
Q-ADC
• Traditional technique
Det chan
• Gated charge ADCs
• Constant Fraction Disc.
• Time-to-Digital Conv.
TDC
Disc.
• High rate applications
Det chan
FADC
Needed: >3 GSPS 12 bit
hits
• Pile-up becomes an issue
 Waveform digitizing
• Issues: Limited speed and
resolution
Trigger
• High channel counts
• Power consumption
• FADC Costs
Moving average baseline
Sept 25th, 2009
CMOS ET Vancouver
3
Switched Capacitor Array
0.2-2 ns
Inverter “Domino” ring chain
IN
Waveform
stored
Clock
Shift Register
Out
FADC
33 MHz
“Time stretcher” GHz  MHz
Sept 25th, 2009
CMOS ET Vancouver
4
DRS4
• Differential inputs,
differential outputs
• Sampling speed
700 MHz … 5 GHz,
PLL stabilized
• Readout speed
30 MHz, multiplexed
or in parallel
Sept 25th, 2009
PLL
WSRIN
DENABLE
DWRITE
REFCLK
IN0
DTAP A0 A1 A2 A3
LVDS
DOMINO WAVE CIRCUIT
MUX
CHANNEL 0
OUT0
CHANNEL 1
OUT1
CHANNEL 2
OUT2
CHANNEL 3
OUT3
CHANNEL 4
OUT4
CHANNEL 5
OUT5
CHANNEL 6
OUT6
IN7
CHANNEL 7
OUT7
IN8
CHANNEL 8
IN1
IN2
IN3
IN4
IN5
IN6
WRITE CONFIG REGISTER
• 8+1 ch. each 1024 cells
AGND AVDD DSPEED PLLOUT PLLLCK
ENABLE
• UMC 0.25 mm
1P5M MMC process
(UMC), 5 x 5 mm2,
radiation hard
FUNCTIONAL BLOCK DIAGRAM
WRITE SHIFT REGISTER
• Designed for the MEG
experiment at PSI,
Switzerland
WSROUT
STOP SHIFT REGISTER
RSRLOAD
SRIN
SRCLK
READ SHIFT REGISTER
MUX
OUT8/
MUXOUT
O-OFS
BIAS
ROFS
SROUT
RESET
CONFIG REGISTER
DVDD DGND
CMOS ET Vancouver
5
Comparison with other chips
MATACQ
D. Breton
LABRADOR
G. Varner
DRS4
this talk
Bandwidth (-3db)
300 MHz
> 1000 MHz
950 MHz
Sampling frequency
50 MHz…2 GHz 10 MHz … 3.5 GHz
700 MHz … 6 GHz
Full scale range
±0.5 V
+0.4 …2.1 V
±0.5 V
Effective #bits
12 bit
10 bit
11.5 bit
Sample points
1 x 2520
9 x 256
9 x 1024
Frequency PLL
YES
NO
YES
Digitization
5 MHz
N/A
30 MHz
Readout dead time
650 ms
150 ms
3 ms – 370 ms
Integral nonlinearity ± 0.1 %
± 0.1 %
± 0.05%
Radiation hard
No
No
Yes (chip)
Board
V1729 (CAEN)
-
V17xx (CAEN)
Sept 25th, 2009
CMOS ET Vancouver
6
Switched Capacitor Array
• Pros (DRS4 chip)
• High speed (5 GHz) high resolution (11.5 bit resol.)
• High channel density (9 channels on 5x5 mm2)
• Low power (10-40 mW / channel)
• Low cost (~ 10$ / channel)
• Cons
• No continuous acquisition
Dt
Dt
Dt
Dt
Dt
• Limited sampling depth
• Nonlinear timing
Sept 25th, 2009
CMOS ET Vancouver
7
How to minimize dead time ?
• Fast analog readout: 30 ns / sample
• Parallel readout
• Region-of-interest
readout
AGND AVDD DSPEED PLLOUT PLLLCK
PLL
WSRIN
DENABLE
DWRITE
REFCLK
LVDS
DOMINO WAVE CIRCUIT
IN0
DTAP A0 A1 A2 A3
MUX
ENABLE
• Simultaneous
write / read
FUNCTIONAL BLOCK DIAGRAM
CHANNEL 1
OUT1
CHANNEL 2
OUT2
CHANNEL 3
OUT3
CHANNEL 4
OUT4
CHANNEL 5
OUT5
CHANNEL 6
OUT6
IN7
CHANNEL 7
OUT7
IN8
CHANNEL 8
IN1
IN2
IN3
IN4
IN5
IN6
WRITE SHIFT REGISTER
OUT0
WRITE CONFIG REGISTER
CHANNEL 0
WSROUT
STOP SHIFT REGISTER
RSRLOAD
SRIN
SRCLK
READ SHIFT REGISTER
MUX
AD9222
12 bit
8 channels
OUT8/
MUXOUT
O-OFS
BIAS
ROFS
SROUT
RESET
CONFIG REGISTER
DVDD DGND
Sept 25th, 2009
CMOS ET Vancouver
8
ROI readout mode
delayed trigger
normal
stop
trigger stop after latency
Trigger
Delay
stop
33 MHz
e.g. 100 samples @ 33 MHz
 3 us dead time
 300,000 events / sec.
Sept 25th, 2009
readout shift register
Patent pending!
CMOS ET Vancouver
9
Daisy-chaining of channels
Domino Wave
clock
Domino Wave
clock
1
enable
input
Channel 0
0
enable
input
Channel 0
0
enable
input
Channel 1
1
enable
input
Channel 1
1
Channel 2
0
Channel 2
0
Channel 3
1
Channel 3
1
Channel 4
0
Channel 4
0
Channel 5
1
Channel 5
1
Channel 6
0
Channel 6
0
Channel 7
1
Channel 7
DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cells
Chip daisy-chaining possible to reach virtually unlimited sampling depth
Sept 25th, 2009
CMOS ET Vancouver
10
Simultaneous Write/Read
FPGA
0
1
Channel 0
0
1
Channel 1
1
0
Channel 2
0
Channel 3
0
Channel 4
0
Channel 5
0
Channel 6
0
Channel 7
readout
8-fold
analog multi-event
buffer
Expected crosstalk ~few mV
Sept 25th, 2009
CMOS ET Vancouver
11
Interleaved sampling
delays (167ps/8 = 21ps)
6 GSPS * 8 = 48 GSPS
G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007)
Possible with DRS4 if delay is implemented on PCB
Sept 25th, 2009
CMOS ET Vancouver
12
Trigger and DAQ on same board
DRS4
trigger
DRS
MUX
• DRS readout (5 GHz samples)
though same 8-channel
FADCs
analog front end
• FPGA can make local trigger
(or global one) and stop DRS
upon a trigger
FADC
12 bit
65 MHz
FPGA
global trigger bus
• Using a multiplexer in DRS4, input signals can simultaneously digitized
at 65 MHz and sampled in the DRS
LVDS
SRAM
“Free” local trigger capability without additional hardware
Sept 25th, 2009
CMOS ET Vancouver
13
Performance of SCA Chips
Test Results
Bandwidth
• Passive Input: Bandwidth is determined by bond
wire and internal bus resistance/capacitance:
850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip)
• Active Inputs: ~300 MHz with current
CMOS technology (MATACQ)
QFP package
• Near future: 130 nm technology
might improve this slightly
850 MHz (-3dB)
Measurement
Sept 25th, 2009
CMOS ET Vancouver
15
Timing jitter
• Inverter chain has transistor
variations
 Dti between samples differ
 “Fixed pattern aperture jitter”
• “Differential temporal nonlinearity”
TDi= Dti – Dtnominal
• “Integral temporal nonlinearity”
TIi = SDti – iDtnominal
• “Random aperture jitter” = variation
of Dti between measurements
Dt1 Dt2 Dt3 Dt4 Dt5
TD1
Sept 25th, 2009
TI5
CMOS ET Vancouver
16
Fixed jitter calibration
• Fixed jitter is constant over time,
can be measured and corrected
for
• Several methods are commonly
used
• Most use sine wave with random
phase and correct for TDi on a
statistical basis
Sept 25th, 2009
CMOS ET Vancouver
17
Fixed Pattern Jitter Results
• TDi typically ~50 ps RMS @ 5 GHz
• TIi goes up to ~600 ps
• Jitter is mostly constant over time,
 measured and corrected
• Residual random jitter (RMS)
• 25 ps MATACQ
• 10 ps Labrador
• 3-4 ps DRS4
 SCA technology can
replace high resolution TDCs
Sept 25th, 2009
CMOS ET Vancouver
18
Applications of SCA Chips
What can we do with this technology?
On-line waveform display
S848
PMTs
“virtual oscilloscope”
template
fit
click
pedestal
histo
Sept 25th, 2009
CMOS ET Vancouver
20
Pulse shape discrimination
Example: a/g source in liquid xenon detector (or: g/p in air shower)
a
g
(t  t 0 ) /τ s
(t  t 0 )/τ d 
 (t  t 0 ) /τi
V(t)  A e
 Be
 Ce
θ(t  t 0 )  [...]θ..  t 0  t r )


Leading edge
Sept 25th, 2009
Decay time
AC-coupling
CMOS ET Vancouver
Reflections
21
t-distribution
ta = 21 ns
tg = 34 ns
a
Waveforms can
be clearly
distinguished
g
Sept 25th, 2009
CMOS ET Vancouver
22
Template Fit
• Determine “standard” PMT pulse by
averaging over many events  “Template”
pb Experiment
500 MHz sampling
• Find hit in waveform
• Shift (“TDC”) and scale (“ADC”)
template to hit
• Minimize c2
• Compare fit with waveform
• Repeat if above threshold
• Store ADC & TDC values
Pile-up can be detected if two hits are
separated in time by ~rise time of signal
Sept 25th, 2009
CMOS ET Vancouver
23
Experiments using DRS chip
MEG 3000 channels DRS4
MAGIC-II 400 channels DRS2
BPM for [email protected]
1000 channels DRS4 (planned)
MACE (India) 400 channels DRS4 (planned)
Sept 25th, 2009
CMOS ET Vancouver
PET
24
Datasheet
http://drs.web.psi.ch/datasheets
Sept 25th, 2009
CMOS ET Vancouver
25
Evaluation Board
• DRS4 can be obtained from PSI on a “non-profit” basis
• Delivery “as-is”
• Costs ~ 15-20 CAN$/chn
• USB Evaluation board as
reference design
• Anybody wants to build a
pocket scope?
Sept 25th, 2009
CMOS ET Vancouver
26
Conclusions
• This is Exciting Stuff!
• DRS4 has 6 GHz, 1024 sampling cells per channel, 9
channels per chip, 11.5 bit vertical resolution, 4 ps timing
accuracy, other chips similar
• More development in the pipeline
• Fast waveform digitizing with SCA chips will have a big
impact on particle detection in the next future
• Other fields should benefit from this development
LABRADOR: http://www.phys.hawaii.edu/~idlab/
MATACQ:
http://matacq.free.fr/
DRS4:
http://drs.web.psi.ch
Sept 25th, 2009
CMOS ET Vancouver
27

similar documents