Secrets of the DCM: Part 1 - Prevailing Technology, Inc.

Report
Secrets of the
DCM: Part 1
Steve Knapp
General Products Division
([email protected])
スティーブ・ナップ
NOTICE:
This is an early draft of this presentation.
Please visit the Xilinx Sales Partner Web
(SPW) for the latest version.
http://www.partner.xilinx.com/common/spartan3/faeconf.htm
© 2004 by Xilinx, Inc. All rights reserved.
(v1.2, 11-OCT-2004)
Workshop Objectives
By the end of this class, you will …
• Understand the function and application of Digital
Clock Managers (DCMs)
• Unlock a few mysteries on how DCMs operate
– More mysteries revealed in Part II
• Become a Clock Wizard and easily configure a DCM
• Have a few new approaches to teach customers on
DCMs
• Legitimately say “DCMs Don’t Confuse Me”
Secrets of the DCM (Part I) 2
Up the Learning Curve
Expertise
Real-World Experience
Part II
Part I
What’s a DCM?
Time
Secrets of the DCM (Part I) 3
DCMs Everywhere!
• In this presentation, the Spartan-3 DCM
demonstrates basic principals and concepts
• The Spartan-3 DCM is similar to Virtex-II and
Virtex-II Pro
• The DLL in the DCM is similar to the DLL in
Virtex/E and Spartan-II/E
• Virtex-4 DCM also employees similar concepts
Secrets of the DCM (Part I) 4
DCMs: The Clock
Problem Solver
Eliminate clock skew—improved performance!
Multiply or divide an incoming clock or create a
completely new clock frequency
Phase shift a clock
Condition a clock input to create 50% duty cycle
Any or all of the above, simultaneously!
 Don’t need it? Then don’t use it!
Secrets of the DCM (Part I) 5
DCM, Where Are You?
XC3S50 only
• Located at top and bottom of
block RAM/multiplier
column(s)
• Four DCMs in each Spartan3, except XC3S50, which has
two DCM
• DCMs have direct
connections to global buffers
along the same edge
• Each DCM has a unique
location string
– Watch PAR placement!
Secrets of the DCM (Part I) 6
DCM_X0Y1
Global buffer multiplexers
DCM_X1Y1
Block RAM
Column
Embedded
Multiplier
Column
DCM_X0Y0
Global buffer multiplexers
DCM_X1Y0
DCM Block Diagram
Delay-Locked Loop (DLL)
Output Stage
Delay Taps
CLKFB
Input Stage
CLKIN
DCM
Digital
Frequency
Synthesizer
PSEN
PSINCDEC
PSCLK
RST
Secrets of the DCM (Part I) 7
Phase Shifter (PS)
Status Logic
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
CLKFX180
PSDONE
STATUS[7:0]
LOCKED
Up to all nine clock
outputs available
simultaneously
Any four of nine
clock outputs
optionally connect to
global buffers along
same edge
Lesson One
Avoid being
skewed!
The Ideal World
FPGA
A
A
B
C
Secrets of the DCM (Part I) 9
B
C
Other
Device on
Board
SKEW
In the Real World, You’re Skewed
FPGA
A
B
C
Db
Dc
Other
Device on
Board
A
B
C
Db
Dc
Secrets of the DCM (Part I) 10
Two different timing relationships!
No Skew, No Problem
Q
CLK
CLK
Q
Flip-flop Delay
Symbol
TIOCKP
Secrets of the DCM (Part I) 11
-4
1.72 ns
Skew: The Time Thief
Q
CLK
CLK
Q
Flip-flop
Input Buffer
Clock Distribution
Secrets of the DCM (Part I) 12
Symbol
TIOCKP
-4
1.72 ns
TICKOF
4.56 ns
Quick Review: What We Want
FPGA
A
A
B
C
Secrets of the DCM (Part I) 13
B
C
Other
Device on
Board
How Do We Get There?
B
A
C
Other
Device on
Board
A
B
C
Db
Dc
Secrets of the DCM (Part I) 14
What if we provide advance clocks?
The Answer?
Clairvoyant Logic, Of Course!
B
Db
A
Dc
C
Other
Device on
Board
A
B
Db
C
Dc
Secrets of the DCM (Part I) 15
-Db + Db = NO SKEW!
Houston, We Have a Problem
• First Rule of Time Travel: You can’t go backwards!
• Clairvoyant logic does not exist (well, at least not yet)
• Now what!?!
Secrets of the DCM (Part I) 16
Forward Thinking
B
A
C
Clock Period (T)
A
Delay=T - Db
B
C
Secrets of the DCM (Part I) 17
Db
Dc
Delay=T- Dc
Other
Device on
Board
The Tough Questions
• How do you specify the clock period?
• How do you determine the delays for Db and Dc?
• How do you voltage- and temperaturecompensate the design?
You Don’t!
?
Secrets of the DCM (Part I) 18
Classroom Experiments
• Everyone please take out your Delay-Lock Loop (DLL)
simulators
LAB 1: Feedback, frequency and phase locking
LAB 2: Stable, monotonic clock
Secrets of the DCM (Part I) 19
The Magical Delay-Locked
Loop (DLL)
Too Early
ADJUST
Clock
Each of the 256
taps is between 30
to 60 ps
Feedback
Delay Line
Clock
Feedback
Phase
Detector
Delay matched Clock and Feedback path lengths
Secrets of the DCM (Part I) 20
The Magical Delay-Locked
Loop (DLL)
Perfect!
Clock
LOCKED
Feedback
Delay Line
Clock
Feedback
Phase
Detector
Delay tap settings updated periodically for temperature/voltage compensation
Update rate controlled by an internal attribute called FACTORY_JF
Secrets of the DCM (Part I) 21
Resulting Timing
Symbol
TIOCKP
TICKOF
TICKOFDCM
Description
-4
1.72 ns
Output flip-flop clock-to-output
Pin-to-pin clock-to-output delay, no DCM 4.56 ns
1.52 ns
Pin-to-pin clock-to-output delay, with
DCM deskew
• ~ 3 ns eliminated from clock distribution delay
when using internal feedback!
• Output delay nearly completely eliminated when
using external feedback
Secrets of the DCM (Part I) 22
Locking
• The DLL requires a stable monotonic clock input
– Stable clock frequency
– Minimal jitter
• The DCM LOCKED output indicates when the DCM has
acquired and locked to the incoming clock
– Application should ignore the DCM clock outputs until LOCKED
asserted
• No clock edges can be missing during the locking process
• If clock is not yet stable, hold the DCM in reset
– External enabled oscillators
– External frequency scaling
– Cascaded DCMs
Secrets of the DCM (Part I) 23
Locking Process
FPGA Configuration
Startup Phase
RST Input
Asserted
LOCKED output
is LOW
If CLKIN not yet stable,
assert RST input until
CLKIN stabilizes.
Is CLKIN
stable? Within
specified limits?
Y
FPGA application
asserts RST input
If lock is lost, assert RST
input to force DCM to
reacquire lock.
Phase
aligned?
Output clocks
good?
Y
LOCKED output
is HIGH
Secrets of the DCM (Part I) 24
N
N
Lost lock.
LOCKED output
is LOW
LOCKED and STATUS Bits
• LOCKED (Output clocks good)
–
–
–
–
The DCM clock outputs are not valid until LOCKED=1
If LOCKED  0, reset the DCM (hit delay tap limits)
It is possible for LOCKED=1 but the output clocks are invalid
STATUS bits provide additional detail
• STATUS[1] – CLKIN Stopped
– STATUS[1]=1 if CLKIN stops toggling, reset the DCM
• STATUS[2] – CLKFX, CLKFX180 Stopped
– STATUS[2]=1 if CLKFX or CLKFX180 outputs stop, and these
outputs are used in the design, reset the DCM
Secrets of the DCM (Part I) 25
Feedback from a Reliable Source
• DLL requires feedback from one of two DCM
outputs
– CLK0 (1X feedback)
– CLK2X (2X feedback)
• CLK2X not presently available on all devices
– Presently supported only on XC3S50 and XC3S1000
– Coming to the remainder of the family in 2005
– Not supported in Virtex-II Pro
Secrets of the DCM (Part I) 26
DCMs Integrate into
FPGA Clock Path
IBUFG
BUFG
PAD
IBUFG
DCM
CLKIN
PAD
Secrets of the DCM (Part I) 27
CLKFB
BUFG
CLKx
Internal Feedback
(or BUFGMUX,
or BUFGCE)
IBUFG
I
O
(alternate clock inputs
possible, but not fully
skew adjusted)
BUFG
CLKIN
CLK0
(or CLK2X)
DCM
CLKFB
LOCKED
(Internal Feedback)
Secrets of the DCM (Part I) 28
I
O
Clock to
internal
FPGA logic
External Feedback
FPGA
IBUFG
I
OBUF
O
CLKIN
IBUFG
I
CLK0
(or CLK2X)
DCM
O
CLKFB
LOCKED
I
O
Circuit-board trace
delay, additional
clock buffers, etc.
Other
Device(s)
on Board
CLK
OBUF
I
O
ENABLE
SRL16
D
Q
RESET
WCLK
A[3:0]
INIT=000F
(External Feedback Trace)
Delay matched Clock and Feedback path lengths
Secrets of the DCM (Part I) 29
Clock Wizard Makes it Easy!
Secrets of the DCM (Part I) 30
Lesson Two
Wizard School
DCM Rules and Lots of Them
The variable phase shifter uses
the PSEN, PSINCDEC, PSCLK,
PSDONE, and STATUS bits
The DLL feedback must come
from either CLK0 or CLK2X.
The CLK2X feedback does not
work for all devices
Secrets of the DCM (Part I) 32
DCM Rule #1
DCM
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
DSSEN
CLKFX
CLKFX180
RST
PSEN
PSINCDEC
PSCLK
Secrets of the DCM (Part I) 33
• All DCMs in a design
must be instantiated
• Language Templates
available in ISE
• Clock Wizard makes it
easy
STATUS[7:0]
LOCKED
PSDONE
Schematic of DCM Example
DCM
IBUFG
33 MHz
BUFG
CLKIN
CLK0
CLKFB
CLK90
33 MHz
CLK180
CLK270
CLK2X
CLK2X180
3.3 MHz
CLKDV
CLKFX
CLKFX180
RST
PSEN
STATUS
PSINCDEC LOCKED
PSCLK
Secrets of the DCM (Part I) 34
PSDONE
BUFG
87 MHz
CLK_FEEDBACK = 1X
CLKDV_DIVIDE = 10
CLKFX_MULTIPLY = 29
CLKFX_DIVIDE = 11
CLKOUT_PHASE_SHIFT = VARIABLE
DFS_FREQUENCY_MODE = LOW
DLL_FREQUENCY_MODE = LOW
PHASE_SHIFT = 23
ISE 6.3i Clock Wizard
Clock Wizard
Graphically configure a
Digital Clock Manager
(DCM)
Vendor-specific
VHDL or Verilog
VHDL or Verilog
instatiation
template
Xilinx Architecture
Wizard (XAW)
settings file
User constraints
file (UCF)
Greatly simplifies using a DCM!
Secrets of the DCM (Part I) 35
Two Methods to Invoke
Clock Wizard
• From Window Start menu
– Start  Xilinx ISE 6  Accessories 
Architecture Wizard
• From within Project Navigator
– Project  New Source
Secrets of the DCM (Part I) 36
Project Navigator Method
New Source
User Document
VHDL Module
IP (CorGen & Architecture Wizard)
Schematic
VHDL Library
VHDL Package
VHDL Test Bench
Test Bench
Waveform
Choose
IP (CoreGen &
BMM File
Architecture Wizard)
MEM File
Implementation Constraints File
State Diagram
< Back
Next >
Click Next to
continue
Secrets of the DCM (Part I) 37
Enter the filename to
save the settings for this
DCM module
File Name:
My_Spartan-3
Location:
MyDirectory
...
Add to Project
Cancel
Help
Click here to select the
directory for the
filename
Selecting the Right Wizard
Select Core Type
Architecture Selection Wizard
Select the wizard:
Architecture Wizards for Spartan-3
Clocking Wizard
Single DCM
Clock Forwarding / Board Deskew
Board Deskew with an Internal Deskew
Clock Switching with Two DCMs
Cascading in Series with Two DCMs
OK
Cancel
(a) Architecture Wizard Accessory
Basic Elements
Clocking
Board Deskew with an Internal Deskew
Cascading in Series with Two DCMs
Clock Forwarding / Board Deskew
Clock Switching with Two DCMs
Single DCM
Communications & Networking
Digital Signal Processing
Architecture Wizard: Single DCM
< Back
Next >
Cancel
(b) IP (CoreGen & Architecture Wizard)
Secrets of the DCM (Part I) 38
Help
General Setup
Xilinx Clocking Wizard - General Setup
CLKIN
CLKFB
RST
PSEN
PSINCDEC
PSCLK
Enter input clock
frequency, with
full accuracy, in
MHz or ns
Selecting External
automatically connects
CLKIN to an IBUFG global
buffer input primitive.
Select Internal to connect
CLKIN to another source.
If clock or feedback is
External, choose whether
the input is Single-ended or
Differential
Set the frequency divider for
the Clock Divider output,
CLKDV
When checked, the CLK0,
CLK90, CLK180, and
CLK270 outputs have 50%
duty cycle
Input Clock Frequency
33
MHz
ns
DLL_FREQUENCY_MODE
Check CLKDV to enable
the Clock Divider options
Check CLKFX or
CLKFX180 to enable the
Frequency Synthesizer
options
Select Fixed to phase shift
all outputs by the value
defined below. Select
Variable mode to
dynamically adjust phase
shifting using the PSEN,
PSINCDEC, and PSCLK
inputs.
STATUS
LOCKED
PSDONE
Phase Shift
Type: VARIABLE
Value:
23
Sets the Fixed phase shift
value or the initial value for
Variable phase shift mode,
measured as x/256ths of a
2.695 ns 32.344 Degrees
clock period, where x=0 to
CLKOUT_PHASE_SHIFT 255.
PHASE_SHIFT
CLKIN Source
External
Internal
Single
Differential
Feedback Source
External
Internal
Single
Differential
Divide By Value
Feedback Value
CLKDV_DIVIDE
10
1X
2X
CLK_FEEDBACK
Use Duty Cycle Correction
DUTY_CYCLE_CORRECTION
< Back
Click here for
advanced options
DCM attribute name
Secrets of the DCM (Part I) 39
CLK0
CLK90
CLK180
CLK270
CLKDV
CLK2X
CLK2X180
CLKFX
CLKFX180
None
Indicate whether the
feedback is from an
Internal or External source
or None
If clock feedback is
required, is it from the
CLK0 output (1X) or the
CLK2X output (2X)?
Advanced ...
More Info
Next >
Cancel
Click Next to
continue
Click here for help
on this screen
Assigning Global Buffers
By default, Clock
Wizard places
global buffers
(BUFG) on all the
selected DCM
clock outputs
Optionally,
customize how the
DCM clock outputs
connect to the
other FPGA logic
using the grid
below
Global Buffer
Xilinx Clocking Wizard - Clock Buffers
I0
BUFG
O
Clock Buffer Settings
Use Global Buffers for all selected clock outputs
Customize buffers
Add Buffer
Input I0
Input I1
View/Edit Buffer
CLK0
Global Buffer
CLK90
Enabled Buffer
CLK180
CLK90
Clock Mux
CLK270
Local Routing
CLKDV
Lowskewline
Click here for help on
this screen
< Back
Next >
Click Next to
continue
Secrets of the DCM (Part I) 40
Enabled Buffer
For each clock
output, select the
type of buffer
connecting the
signal to the
FPGA
BUFGCE
I0
O
CE
BUFGMUX
I0
O
Clock Mux I1
S
Lowskewline I0
More Info
Cancel
Local Routing I0
Frequency Synthesizer
Xilinx Clocking Wizard - Clock Frequency Synthesizer
CLK0
CLKFX
CLKFX180
If using only the
CLKFX or CLKFX180
clock outputs, uncheck
CLK0 to extend the
DCM frequency limits
Check CLKFX or
CLKFX180 to enable
the Frequency
Synthesizer options
DFS_FREQUENCY_MODE
Valid Ranges for Speed Grade -4
Displays the incoming clock
frequency, specified earlier
DFS
Fin (MHz)
Fout (MHz)
Low
24.000 - 165.000
24.000 - 210.000
High
48.000 - 280.000
210.000 - 280.000
Displays the frequency limits
for the Frequency Synthesizer
in both low- and highfrequency mode
Inputs for Jitter Calculations
Input Clock Frequency: 33.000 MHz
If only using the CLKFX or CLKFX180
clock ouputs, optionally click None to
extend the DCM frequency limits.
Feedback
Source:
Value:
Internal
1X
External
2X
Enter the desired output
frequency, in MHz or ns,
then click Calculate. DCM
Wizard calculates the best
multiply (M) and divide (D)
values possible.
Use output frequency
ns
Use Multiply (M) and Divide (D) values:
M 4
None
(back on General Setup)
MHz
87
Optionally, enter the specific
values for the multiply (M)
and divide (D) values, then
click Calculate
CLKFX_MULTIPLY
After entering the desired
output frequency or multiply
and divide values, click
Calculate to compute the
resulting jitter for the
Frequency Synthesizer output
1
D
CLKFX_DIVIDE
Calculate
Generated Output
CLKFX_MULTIPLY
M
D
Output
Frequency
(MHz)
Period Jitter
(pk-to-pk ns)
Period Jitter
(unit interval)
29
11
87
0.10
1.12
CLKFX_DIVIDE
Click here for help on
this screen
< Back
DCM attribute name
Secrets of the DCM (Part I) 41
Finish
Displays the calculated output
jitter values based on the
settings
More Info
Cancel
Click Finish
when finished
Voila!
Secrets of the DCM (Part I) 42
Instantiation Template
VHDL Example
Click new Clock
Wizard source file
Sources in Project:
xc3s400-4fg456
My_Design (my_design.vhd)
my_dcm (my_dcm.xaw)
Module View
Double click to view
instantiation template
Processes for Source: “my_dcm”


Add Existing Source
Create New Source
Create Schematic Symbol
View HDL Source
View HDL Instantiation Template
COMPONENT my_dcm
PORT (
CLKIN_IN : IN std_logic;
RST_IN : IN std_logic;
LOCKED_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic
);
END COMPONENT;
Inst_my_dcm: my_dcm PORT MAP(
CLKIN_IN => ,
RST_IN => ,
LOCKED_OUT => ,
CLK0_OUT =>
);
Process View
Available for both VHDL and Verilog
Secrets of the DCM (Part I) 43
VHDL
component
declaration
VHDL
component
instantiation
Lesson Three
Jitter
What is Jitter?
Number of samples
Ideal Clock
Measured clock period
Peak-to-peak Period Jitter
• Uncertainty on exact timing of a clock edge
• Affected by power noise, decoupling, SSOs, internal
switching, etc.
• Period (peak-to-peak) jitter specification is most quoted
– Specified as either absolute (300 ps) or deviation (± 150 ps)
Secrets of the DCM (Part I) 45
Clock Jitter Specifications
• Period (peak-to-peak) jitter
• Cycle-to-cycle jitter
T1=T0+100 ps
T0
• Unit Interval (UI)
Peak-to-peak
Period Jitter
T2=T1-150 ps
Example
UI=0.10 means that
period jitter is 10% of
the total bit period
Bit Period
Unit Interval (UI)
Secrets of the DCM (Part I) 46
Peak-to-peak period jitter,
represented as fraction of
Unit Interval
Jitter Effects on Cycle Timing
Single Data Rate (SDR)
Earliest
Arrival
Available Period
Clock Period
Bit Period
Secrets of the DCM (Part I) 47
Half
Period
Jitter
Jitter Effects on Cycle Timing
Double Data Rate (DDR)
Available
Period
Earliest
Arrival
Available
Period
Consider both clock
edges in DDR
applications
Jitter
Bit Period
No duty-cycle distortion
effects considered
Secrets of the DCM (Part I) 48
Clock Period
Jitter Effects on Flip-Flop Timing
Early Clock Edge
Half
Period
Jitter
• Increases input set-up time
• Reduces minimum clock-tooutput time
Secrets of the DCM (Part I) 49
Late Clock Edge
Half
Period
Jitter
• Increases hold time
• Increases maximum clock-tooutput time
Minimizing Clock Jitter
• Switching noise causes jitter
– Proper power, PCB design, and decoupling
• XAPP623: Power System Distribution Guidelines
http://www.xilinx.com/xapp/xapp623.pdf
• PCB Checklist
http://support.xilinx.com/products/design_resources/highspeed_design/si_pcbcheck.htm
– % CLB switching contributes noise
– Obey SSO recommendations (in Spartan-3 data sheet)
• VCCAUX is voltage source for DCMs
• GND pins for logic and DCMs are common
• Jitter on input clock
– Garbage in, garbage out
• Take care of your clocks and your clocks will take care of you
Secrets of the DCM (Part I) 50
GOVERNMENT HEALTH WARNING:
FAILING TO APPLY XAPP623 COULD BE
HAZARDOUS TO YOUR DCM DESIGN AND
YOUR MENTAL HEALTH
Secrets of the DCM (Part I) 51
XAPP462: The DCM Reference
• A comprehensive 68page “tree killer”
• Updated for ISE 6.3i and
latest Spartan-3 DCM
knowledge
www.xilinx.com/bvdocs/appnotes/xapp462.pdf
Secrets of the DCM (Part I) 52
Second Verse, Same as the First*
• If you enjoyed this session, please also attend …
Secrets of the DCM
Part II
* Only a little bit louder and a whole lot worse
Secrets of the DCM (Part I) 53
Questions?
[email protected]
Secrets of the DCM (Part I) 54
Please Fill Out and Return the
Feedback Forms!
• Forms are in the back of your FAE conference book
• Please return at back of the room
Secrets of the DCM: Part 1
Steve Knapp



Secrets of the DCM (Part I) 55
Jump Point
• Overview
• Lesson 1: Avoid Being Skewed
• Lesson 2: Clock Wizard School
• Lesson 3: Clock Jitter
• Session Evaluation Forms
Return to last slide viewed
Secrets of the DCM (Part I) 56

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