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System on Chip (SoC) Architecture Design
SOCks – FPU Example
James E. Stine
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CADENCE DESIGN SYSTEMS, INC.
Structure of Floating Point Multiplier
All calculations are done
in double precision
Single-to-Double
conversion
Mantissa
Sign
Dadda Multiplier
Exponent
Sticky Bit
Postnormalization
Rounding
Output
3
Dadda Multiplier
Partial Products
Compression
(Half Adder)
Compression
(Full Adder)
Final Carry-Propagate Adder
4
AMBA Interface
Arbiter
Address and
Control Mux
HADDR
HADDR
HWDATA
MASTER 1,
LEON
HWDATA
SLAVE 1,
Floating
Point Unit
HRDATA
HRDATA
Address =
0xA016_0000
HADDR
HWDATA
MASTER n
HADDR
HWDATA
SLAVE n
HRDATA
HRDATA
Read Data
Mux
Decoder
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The Floating Point Unit is interfaced with the
LEON through the AHB AMBA interface
(Advanced High-Performance Bus).
This bus is intended to provide a high-speed
communication with the processor.
AMBA Interface
A typical AMBA AHB system includes:
• AHB Master: Initiates read or write operations on the bus. Only one
Master is allowed to access the bus at a time.
• AHB Slave: AHB Slave responds to a read or write, given an addressspace range. It then responds with acknowledge, wait or fail signal to
the requesting master.
• AHB Arbiter: The arbiter is responsible for allowing access to the bus
to only one Master at any time. The arbitration algorithm may be
modified.
• AHB Decoder: A single decoder is required for all AHB devices. It is
used to decode the address of each transfer and provide a select
signal for the involved slave in that transfer.
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AMBA AHB / FPU Interface
Data input from CPU
match_FPSCR address & Write Enable
(write to FPSCR?)
[26:0]
27
1
FPSCR Register
FLAGS
FSM Control
SP/DP
Result OpB OpA
[31:27] [26:16] [15] [14:10] [9:5] [4:0]
FPSCR_OUT, [19:16]
Traps, SP/DP, Rounding, etc
1
FPSCR Out
fpu_CPU
Address input from
CPU
32
0
Address
Input
(0-31)
1
Data input from
CPU
32
0
1
Operand A
Address
0
32
fpu_CPU
1
FPSCR Out
Operand B
Address
Register File 32 x
32-bit
Operand A
Data
7
5
1
64
From FSM
Control
4
32
AMBA Module address
match & CPU Write Enable
Operand B
Data
64
FPSCR Address match
(fpscr_match)
1
Data Input
extended 32-bits
(double precision)
Data Output
(CPU Read)
32
5
Write Enable
Data Input
(CPU Write)
1
Data output
to CPU
5
Single/Double
Precision
Bit [15]
From FPSCR output
[19:16]
Floating Point
Traps, Round
Unit
Mode, SP/DP
Result
[63:32]
[31:0]
FLAGS
(Invalid, UDF, OVF,
Inexact, DivZero)
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SOCks FP Multiplier
Step-by-step
• Check if sufficient disk space is available
“quota –v”
• Get SOCks kit and install it
(package created by Johannes Grad from Illinois Institute of Technology)
“tar xvf /import/vlsi7/jgrad/socks/socks.tar”
• Make sure that RTEMS is installed
(Real-Time Operating System for Multiprocessor Systems)
• Set the path to RTEMS
“set path = (/opt/rtems/bin $path)”
• Test if the path was added
“which sparc-rtems-g++”
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SOCks FP Multiplier
Step-by-step
• Go to ./firmware directory
“cd ./firmware”
• Create a new source code folder by copying other example to a
new directory.
“cp –r bubblesort project_name”
• Modify main test file (leon_test.c) and other necessary files
(misc.c, test.h, leon.h). Additional modifications were necessary
because additional structure vint was introduced.
• Compile the firmware
“make”
• After successful compilation go to HDL custom directory.
“cd ../../hdl/custom”
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SOCks FP Multiplier
Step-by-step
• Digital Logic stored in HDL/custom directory communicates with
Leon processor through AMBA bus.
• Put FPU files in custom directory.
• Compiler is set to compile all Verilog files that are stored in
hdl/custom directory. In this case VHDL was used so change
was necessary. Following line was added to exe/socks_compile
“ncvhdl –v93 –work customlib ./custom/*.vhd”
• Go to HDL directory
“cd ..”
• Compile the custom logic HDL
In this context compilation means building a HDL simulation
model, not a binary code as in C++ compilation.
“../exe/socks_compile”
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SOCks FP Multiplier
Step-by-step
• After successful HDL compilation go to sim directory
“cd ../sim”
• Run the simulation
– “../exe/socks_sim project_name”
– “../exe/socks_sim project_name partial”
(creates waveforms for the custom logic)
– “../exe/socks_sim project_name full”
(creates waveforms for the entire design)
• View the waveforms if needed
“simvision &”
• Remove temporary files to save space
“cd ..”
“exe/socks_clean”
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SOCks FP Multiplier
Step-by-step
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SOCks FP Multiplier
Step-by-step
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SOCks FP Multiplier
Step-by-step
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SOCks FP Multiplier
Step-by-step
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SOCks FP Multiplier
Step-by-step
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