Design Space Exploration of Embedded Systems

Report
Design Space Exploration
of Embedded Systems
© Lothar Thiele
ETH Zurich
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Overview
Review of General Aspects
Basic Models and Methods
Modular Performance Analysis
Multi-Criteria Optimization
Applications
Concluding Remarks
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Target Platform
Heterogeneous computing and memory resources
• some resource types: GP processors, ASIPs (DSP,
micro-controller), weakly programmable coprocessors, re-configurable components, hard
coded IP components
image
coprocessor
SDRAM
mC
DSP
FPGA
RISC
CAN
interface
• heterogeneous platform software: RTOS,
scheduling (pre-emptive, static, dynamic),
synchronization
Swiss Federal
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Computer Engineering
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Target Platform
Communication
• micro-network on chip for synchronization and
data exchange consisting of busses, routers,
drivers
• some critical issues: topology, switching strategies
(packet, circuit), routing strategies (static –
reconfigurable – dynamic), arbitration policies
(dynamic, TDM, CDMA, fixed priority)
• challenges: heterogeneous components and
requirements, compose network that matches the
traffic characteristics of a given application
(domain)
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Computer Engineering
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Design Space
Scheduling/Arbitration
Computation Templates
Communication Templates
Cipher
EDF
FPGA
RISC
SDRAM
WFQ
DSP
DSP
Which architecture is better suited
LookUp
mE
for our application?
RISC
EDF
mE
TDMA
DSP
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dynamic
fixed priority
FCFS
static
mE
mE
static
Priority
Cipher
proportional
share
Architecture # 2
Architecture # 1
LookUp
TDMA
mE
WFQ
‹#›
mE
mE
Computer Engineering
and Networks Laboratory
Design Space Exploration
Application
Architecture
Mapping
Analysis
This process takes place on several
levels of abstraction.
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Design Space Exploration
Application
Architecture
Mapping
Analysis
This talk: Exploration and Analysis
on a high level of abstraction.
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Design Space Exploration
Application
Architecture
Mapping
Analysis
(Semi-) Automated
Design Space
Exploration
This talk: Exploration and Analysis
on a high level of abstraction.
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Why is Performance Analysis Difficult?
task1
complex behavior
- input stream
- data dependent behavior
interference
task2
task3
CPU1
I/O
CPU2
DSP
task4
- limited resources
- scheduling/arbitration
interference of multiple
applications
- limited resources
- scheduling/arbitration
- anomalies
Swiss Federal
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Computer Engineering
and Networks Laboratory
Simulation
Target architecture co-simulation
• combines functional and performance validation
• extensive runtimes
• worst case inputs ?
• test case definition ?
• re-targeting expensive
mixed model
input
trace
Swiss Federal
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function:
structure:
application
hardware-software
architecture
‹#›
output
trace
Computer Engineering
and Networks Laboratory
Trace-Based Simulation
Steps:
• execution trace determined by co-simulation
• abstract representation using communication graph
• extension of graph by actual architecture
Faster than simulation, but still based on single trace
input
trace
functional
model
[Lahiri et. al, 2001]
Swiss Federal
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complete
trace
abstract
graph
communication
architecture
trace
simulation
‹#›
estimation
results
Computer Engineering
and Networks Laboratory
Static Analytic Models
Steps:
• describe computing, communication and memory
resources by algebraic equations, e.g.
 # words 
delay  
comm_ tim e

 burst _ size 
• describe properties of input using parameters, e.g.
input data rate
• combine relations
Fast and simple estimation
Generally inaccurate modeling of shared resources
Swiss Federal
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Computer Engineering
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Dynamic Analytic Models
Combination between
• static models, possibly extended by their dynamic
behavior, e.g. non-determinism in run-time and
event processing
• dynamic models for describing shared resources
(scheduling and arbitration)
Variants
• queuing theory (statistical models, average case)
• real-time calculus (interval methods, worst case)
More accurate than static models
Swiss Federal
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Computer Engineering
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Dynamic Analytic Models
component
simulation
input
traces
spec. of
inputs
data
sheets
model of
components
model of
environment
system
model
model of
architecture
estimation
results
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Overview
Review of General Aspects
Basic Models and Methods
Modular Performance Analysis
Multi-Criteria Optimization
Applications
Concluding Remarks
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Examples Event Stream Processing
©UCB Rabaey
Embedded
Internet
Devices
method (a)(fsd)
for I=1 to n
do nothing
call comm(a,dsf,*e);
end for
Wearable Computing
Core
Access
Mobile Internet
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Computer Engineering
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Application Model
Example of a simple stream processing task structure:
Swiss Federal
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Computer Engineering
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Architecture Templates
In general, we assume an arbitrary heterogeneous
architecture consisting of computing resources,
memory and communication resources.
event
event
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‹#›
events
Computer Engineering
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Mapping Model
Swiss Federal
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Computer Engineering
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Abstraction
Idea:
• unified view of task scheduling, arbitration and
event scheduling in networks:
• methods:
• queueing theory (statistical bounds, markov chains)
• real-time calculus (worst case bounds, min-max algebra)
Swiss Federal
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Computer Engineering
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Real-Time Calculus
Example of a dynamic analytic model
Characteristics
• yields worst case estimation results for memory,
delay, throughput
• takes into account
• application structure (task graph representation, SPI)
• architecture and mapping (computation, communication,
scheduling)
• environment (characterization of input traces)
Swiss Federal
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‹#›
Computer Engineering
and Networks Laboratory
Foundations of Real-Time-Calculus
Linear System Theory [Baccelli, Cohen, Olsder,
Quadrat 1992]
Calculus for Networks [Le Boudec 1998, 2001],
[Cruz 1991]
Adversarial Queuing Theory [Andrews, Borodin,
Kleinberg, Leighton, … 1996]
Competing Approaches:
• SymTA/S: [R. Ernst et. al. 2002]
• Holistic Scheduling: [P. Eles 1999]
• Distributed Scheduling: [Tindell, Burns 1996]
• Recurring Task Models: [S. Baruah, 1998, 2002]
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Overview
Review of General Aspects
Basic Models and Methods
Modular Performance Analysis
Multi-Criteria Optimization
Applications
Concluding Remarks
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Elements of Modular Performance Analysis
application
hardware architecture
mapping, scheduling
system
architecture
model
environment
model
performance
model
architectural
element
model
analysis
Swiss Federal
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‹#›
Computer Engineering
and Networks Laboratory
Event Streams (Environment Model)
How do we model uncertain event streams?
time t [ms]
Event Stream
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Computer Engineering
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Event Streams (Environment Model)
Use interval bound functions: Arrival Curves
time t [ms]
Event Stream
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Computer Engineering
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Event Streams (Environment Model)
Use interval bound functions: Arrival Curves
# of events
max: 321 events
event
maximum/minimum
min: 10 events
number of events in any
interval of length 2.5 ms
au
3
al
2
1
D DD
time t [ms]
1
D [ms]
2
Arrival Curves [al, au]
Event Stream
Swiss Federal
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0
‹#›
Computer Engineering
and Networks Laboratory
Elements of Modular Performance Analysis
application
hardware architecture
mapping, scheduling
system
architecture
model
environment
model
performance
model
architectural
element
model
analysis
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Resources (Architectural Element Model)
Use interval bound functions: Service Curves
maximum/minimum
available service in any
interval of length 2.5 ms
service
bu
availability
bl
3
2 and
Works for computation
1
communication resources!
0
t [ms]
D [ms]
2
Service Curves [bl, bu]
Service Availability
Swiss Federal
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1
‹#›
Computer Engineering
and Networks Laboratory
Arrival and Service Curves
How can we determine the arrival curves of flows ?
• Derive arrival curves from TSpec (IETF).
• Use given traces (arrival function) and measure.
• Use properties of generating devices.
How can we determine the service curves of
resources (busses, computing devices) ?
• Use data sheet of the component (service
function) and compute.
• Measure or simulate the service under simple load
conditions (service functions) and compute.
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Elements of Modular Performance Analysis
application
hardware architecture
mapping, scheduling
system
architecture
model
environment
model
performance
model
architectural
element
model
analysis
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Application
Application
Swiss Federal
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p=1 s, j=0.2 s
Hndl
‹#›
Dec
Disp
Computer Engineering
and Networks Laboratory
Hardware Architecture
Application
p=1 s, j=0.2 s
Hndl
HW Architecture
Swiss Federal
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22 MIPS
‹#›
Dec
72 kbps
Disp
10 MIPS
Computer Engineering
and Networks Laboratory
Mapping
Application
p=1 s, j=0.2 s
Hndl
Dec
Disp
Mapping
HW Architecture
Swiss Federal
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22 MIPS
‹#›
72 kbps
10 MIPS
Computer Engineering
and Networks Laboratory
Allocation and Binding
Allocation can be represented as a function:
allocation : S  true, false
task1
Binding is a relation:
binding : T  S   true, false
class
task2
filter
task3
schedule
task4
risc
T
Binding restrictions:
t  T s  S : binding(t , s )  true
s  S : binding(t , s )  true  allocation( s )  true
Swiss Federal
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S
Computer Engineering
and Networks Laboratory
Elements of Modular Performance Analysis
application
hardware architecture
mapping, scheduling
system
architecture
model
environment
model
performance
model
architectural
element
model
analysis
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Task Sequence
Application
p=1 s, j=0.2 s
Swiss Federal
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p=1 s, j=0.2 s
Hndl
Dec
Disp
CPU2
CPU
CPU2
Hndl
Dec
Disp
‹#›
Computer Engineering
and Networks Laboratory
Task Sequence
p=1 s, j=0.2 s
Swiss Federal
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CPU2
CPU
CPU2
Hndl
Dec
Disp
‹#›
Computer Engineering
and Networks Laboratory
Task
Performance
Component
l’, au’]
events
[a
l, au]
events
[a
WCETDec
BCETDec
CPU
Dt [ms]
l , bu ]
speed
[b
?
?
Dec
Dec
Dt [ms]
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Dt [ms]
l’, bu’]
speed
[b
Dt [ms]
‹#›
Computer Engineering
and Networks Laboratory
A Simple Building Block
task
event stream
t
event stream
R(t) #events
t
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Computer Engineering
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t
A Simple Building Block
task
event stream
t
event stream
C(t)
event stream
R(t)
resource stream
interaction
R’(t)
C’(t)
Simulation can not detect absence of failures.
Swiss Federal
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‹#›
Computer Engineering
and Networks Laboratory
t
A Simple Building Block
task
event stream
embedding
t
C(t)
event stream
R(t)
resource stream
interaction
R’(t)
C’(t)
resource bound function
event bound function
Swiss Federal
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abstraction
interaction
‹#›
Computer Engineering
and Networks Laboratory
Bound Functions
maximum/minimum
number of events in any
interval of length 4
events
number of events in time
interval [0,4]
Swiss Federal
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Computer Engineering
and Networks Laboratory
Some Basic Facts
: min-plus algebra
is called min-plus convolution as
is called de-convolution as
Many properties are known and results resemble
conventional linear system theory.
Swiss Federal
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Computer Engineering
and Networks Laboratory
Some Basic Facts
From streams to upper bound functions:
An input stream R(t) is constraint by an upper bound
function iff
The output stream of a component satisfies:
The output bound function of a component satisfies:
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Computer Engineering
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Transformation of Curves
[b l , b u ]
[a l , a u ]
[a l  , a u ]
[ b l  , b u ]
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Elements of Modular Performance Analysis
application
hardware architecture
mapping, scheduling
system
architecture
model
environment
model
performance
model
architectural
element
model
analysis
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Performance Model
Application
Application Model
p=1 s, j=0.2 s
Hndl
Dec
Disp
a
Mapping/Scheduling
HW Architecture Model
HW Architecture
Swiss Federal
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b
b
b
CPU1
BUS
CPU2
22 MIPS
‹#›
72 kbps
10 MIPS
Computer Engineering
and Networks Laboratory
Modularity
Resource
How
How
can
can
we
we
can
estimate
we of
add
a HW/OS/SW
athe
resource
new
load
application?
on
components
resources?
component?
?
HowHow
canInterface
wecompose
represent
allocation
strategies?
ES 1
Network
share
a
Application 1
a
Application 2
b
b
FP
GPS
b’
b’
GPS
GPS
b’’
b’’
ES 2
ES 3
b
b
FP
FP
b’
b’
S
Swiss Federal
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Computer Engineering
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Delay and Backlog
bl
[bl, bu]
[al, au]
delay d
[al’, au’]
au
[bl’, bu’]
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backlog b
‹#›
Computer Engineering
and Networks Laboratory
Refined Abstractions using FSMs
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Computer Engineering
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Event Stream Model
a
F
#events vs. time interval
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order of events
‹#›
Computer Engineering
and Networks Laboratory
Functional Unit Model
input_event/resource_demand/output_event
FSM can model
caches and other
architecture details
program flow
type-dependent behavior
Improvement in estimation
quality in several application
studies.
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Modular Performance Analysis
application
hardware architecture
mapping, scheduling
system
architecture
model
environment
model
performance
model
architectural
element
model
analysis
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Overview
Review of General Aspects
Basic Models and Methods
Modular Performance Analysis
Multi-Criteria Optimization
Applications
Concluding Remarks
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Why Performance Analysis?
Application
Architecture
Mapping
Analysis
(Semi-) Automated
Design Space
Exploration
This talk: Exploration and Analysis
on a high level of abstraction.
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Optimization with conflicting goals
Multiobjective optimization: Find a set of optimal trade-offs
• Example: computer design
performance
power
resolution weight
size
cost
conflicts
trade-offs
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Computer Engineering
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Multi-objective Optimization
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Computer Engineering
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Multiobjective Optimization
Maximize (y1, y2, …, yk) = (x1, x2, …, xn)
y2
y2
Pareto optimal = not dominated
better
incomparable
worse
dominated
incomparable
y1
y1
Pareto set = set of all Pareto-optimal solutions
Swiss Federal
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Computer Engineering
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Multiobjective Optimization
(x1, x2, …, xn)
Minimize
f
x2
decision
space
(y1, y2, …, yk)
y2
objective
space
dominated
y1
x1
Difficulties:  large search space
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‹#›
Pareto optimal
=
not dominated
 multiple optima
Computer Engineering
and Networks Laboratory
Optimization Alternatives
Use of classical single objective optimization methods
• simulated annealing, tabu search
• integer linear program
• other constructive or iterative heuristic methods
Decision making (weighting the different objectives)
is done before the optimization.
Population based optimization methods
• evolutionary algorithms
• genetic algorithms
Decision making is done after the optimization.
Swiss Federal
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Computer Engineering
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Traditional Approaches
multiple
objectives
(y1, y2, …, yk)
parameters
transformation
y2
single
objective
y
Example: weighting approach
(w1, w2, …, wk)
y = w1y1 + … + wkyk
y1
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Computer Engineering
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Evolutionary Algorithms
Principles of Evolution
 Selection
 Cross-over
 Mutation
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Computer Engineering
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A Generic Multiobjective EA
population
archive
evaluate
sample
vary
new population
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update
truncate
‹#›
new archive
Computer Engineering
and Networks Laboratory
An Evolutionary Algorithm in Action
max. y2
hypothetical trade-off front
min. y1
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(Our) Areas of Research
Algorithms:
• Improved techniques (distance/diversity tradeoff)
SPEA-2
• Software toolboxes (building blocks)
PISA
Performance Assessment:
• Test problems
• New performance indicators
• Statistical framework for performance assessment
Theory:
• Convergence and diversity proofs
• Performance indicators
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Computer Engineering
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Theoretical results
Which technique is suited for which problem class?
 Theoretically (by analysis): difficult
• Limit behavior (unlimited run-time resources)
• Running time analysis
 Empirically (by simulation): standard
Problems:
Issues:
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randomness, multiple objectives
quality indicators, benchmark problems
‹#›
Computer Engineering
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Running Time Analysis
problem domain
discrete
search
spaces
Single-objective
EAs
continuous
search
spaces
Multiobjective
EAs
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•
type of results
expected RT
(bounds)
[Mühlenbein 92]
[Rudolph 97]
[Droste, Jansen, Wegener 98,02]
[Garnier, Kallel, Schoenauer 99,00]
[He, Yao 01,02]
•
RT with high
probability
(bounds)
•
asymptotic
convergence rates
•
exact convergence
rates
[Beyer 95,96,…]
[Rudolph 97]
[Jagerskupper 03]
[no previous results]
‹#›
Computer Engineering
and Networks Laboratory
What Is Needed…
A framework that
•
•
•
•
Provides ready-to-use modules (algorithms / applications)
Is simple to use
Is independent of programming language and OS
Comes with minimum overhead
Idea: separate problem-dependent from problemindependent part
cut
Selection
Fitness assignment
Representation
Recombination
Archiving
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Objective functions
Mutation
‹#›
Computer Engineering
and Networks Laboratory
A Generic Multiobjective EA
population
problem
dependent
archive
evaluate
sample
vary
new population
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update
truncate
‹#›
new archive
Computer Engineering
and Networks Laboratory
The Concept of PISA
Algorithms
Applications
SPEA2
knapsack
NSGA-II
TSP
PAES
network
processor
design
Platform and programming language independent Interface
for Search Algorithms [Bleuler et al.: 2002]
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Computer Engineering
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PISA: Implementation
shared
file system
selector
process
application independent:
mating / environmental
selection
individuals are described
by IDs and objective
vectors
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text
files
handshake protocol:
state / action
individual IDs
objective vectors
parameters
‹#›
variator
process
application dependent:
variation operators
stores and manages
individuals
Computer Engineering
and Networks Laboratory
PISA Website
http://www.tik.ee.ethz.ch/pisa
Swiss Federal
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Computer Engineering
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Overview
Review of General Aspects
Basic Models and Methods
Modular Performance Analysis
Multi-Criteria Optimization
Applications
Concluding Remarks
Swiss Federal
Institute of Technology
‹#›
Computer Engineering
and Networks Laboratory
Experiences
Network processor modeling (IBM)
• Detailed study of a network processor
• Good match between simulation and analytic
methods (delay, memory)
Use of methodology in other projects and case
studies
• BridgeCo
• Siemens
• Netmodule
Implementation and integration into design space
exploration
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Computer Engineering
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EXPO – Tool architecture
Tool available online:
http://www.tik.ee.ethz.ch/expo/expo.html
MOSES
system architecture
performance values
EXPO
task graph,
scenario graph,
flows & resources
SPEA 2
Exploration
Cycle
selection
of “good” architectures
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Computer Engineering
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Validation Strategy (IBM)
Hardware Components
(bus, bridge, memory, processor)
Simple
workloads
SystemC
Component Models
SystemC
System Model
Complex
workloads
Parameters
Comparison
Traces
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Analytical
Component Models
Analytical
System Model
Arrival Curves
‹#›
Computer Engineering
and Networks Laboratory
Validation Strategy
Hardware Components
(bus, bridge, memory, processor)
Simple
workloads
SystemC
Component Models
SystemC
System Model
Complex
workloads
Parameters
Comparison
Traces
Swiss Federal
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Analytical
Component Models
Analytical
System Model
Arrival Curves
‹#›
Computer Engineering
and Networks Laboratory
Derivation of Analytical Models
Busses (PLB, OPB), Ethernet Core (EMAC), PLB-OPB-Bridge,
Memory based on IBM CoreConnect and Blue Logic Core
Library.
Bus example:
Simple
workloads
SystemC
Simulation
b
C
Byte
Byte
Data Sheets
cycle
Swiss Federal
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‹#›
cycle
Computer Engineering
and Networks Laboratory
Validation Strategy
Hardware Components
(bus, bridge, memory, processor)
Simple
workloads
SystemC
Component Models
SystemC
System Model
Complex
workloads
Parameters
Comparison
Traces
Swiss Federal
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Analytical
Component Models
Analytical
System Model
Arrival Curves
‹#›
Computer Engineering
and Networks Laboratory
From Traces to Arrival Curves
Trace:
packet
cycles
Arrival Curve:
Byte
average rate
max. packet size
longest gap
cycles
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Computer Engineering
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Validation Strategy
Hardware Components
(bus, bridge, memory, processor)
Simple
workloads
SystemC
Component Models
SystemC
System Model
Complex
workloads
Parameters
Comparison
Traces
Swiss Federal
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Analytical
Component Models
Analytical
System Model
Arrival Curves
‹#›
Computer Engineering
and Networks Laboratory
Architecture and Tasks
Swiss Federal
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Computer Engineering
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Validation Strategy
Hardware Components
(bus, bridge, memory, processor)
Simple
workloads
SystemC
Component Models
SystemC
System Model
Complex
workloads
Parameters
Comparison
Traces
Swiss Federal
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Analytical
Component Models
Analytical
System Model
Arrival Curves
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and Networks Laboratory
Analytical System Model
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Validation Strategy
Hardware Components
(bus, bridge, memory, processor)
Simple
workloads
SystemC
Component Models
SystemC
System Model
Complex
workloads
Parameters
Comparison
Traces
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Analytical
Component Models
Analytical
System Model
Arrival Curves
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Computer Engineering
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Comparison
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Computer Engineering
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Application Scenario: In-Car Navigation System
Car radio with navigation system
User interface needs to be responsive
Traffic messages (TMC) must be processed in a timely
way
Several applications may execute concurrently
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System Overview
MMI
Communication
NAV
RAD
DB
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Application 1: Change Audio Volume
< 200 ms
MMI
Communication
NAV
RAD
DB
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Application 1: Change Audio Volume
Communication
Computation
Performance
Input Resource
Data
Resource
Requirements
RateDemand
Demand
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Computer Engineering
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Application 2: Lookup Destination Address
< 200 ms
MMI
Communication
NAV
RAD
DB
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Computer Engineering
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Application 2: Lookup Destination Address
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Computer Engineering
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Application 3: Receive TMC Messages
MMI
Communication
NAV
RAD
DB
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Computer Engineering
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Application 3: Receive TMC Messages
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Computer Engineering
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Proposed Architecture Alternatives
22 MIPS
MMI
(A)
113 MIPS
NAV
72 kbps
(B)
11 MIPS
113 MIPS
11 MIPS
RAD
NAV
RAD
RAD
22 MIPS
MMI
(E)
113 MIPS
NAV
NAV
72 kbps
260 MIPS
57 kbps
MMI
(D)
72 kbps
(C)
22 MIPS
72 kbps
130 MIPS
260 MIPS
RAD
MMI
MMI
RAD
NAV
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Step 1: Environment (Event Steams)
Event Stream Model
e.g. Address Lookup
(1 event / sec)
au
[events]
al
1
1
1
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‹#›
Computer Engineering
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[s]
Step 2: Architectural Elements
Event Stream Model
e.g. Address Lookup
(1 event / sec)
au
[events]
al
1
1
Resource Model
[MIPS]
e.g. unloaded RISC CPU
(113 MIPS)
bl=bu
113
1
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Computer Engineering
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[s]
Step 3: Mapping / Scheduling
Rate Monotonic Scheduling
(Pre-emptive fixed priority scheduling):
• Priority 1:
• Priority 2:
• Priority 3:
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Change Volume
Address Lookup
Receive TMC
‹#›
(p=1/32 s)
(p=1 s)
(p=6 s)
Computer Engineering
and Networks Laboratory
Step 4: Performance Model
CPU1
b
BUS
MMI
b
CPU3
CPU2
b
NAV
b
RAD
a
Change Volume
a
Address Lookup
a
Receive TMC
MMI
NAV
RAD
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Computer Engineering
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Step 5: Analysis
CPU1
b
BUS
MMI
b
CPU3
CPU2
b
NAV
b
RAD
a
Change Volume
a
Address Lookup
Real-Time Calculus
a
Receive TMC
MMI
NAV
RAD
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Computer Engineering
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Analysis – Design Question 1
How do the proposed system architectures
compare in respect to end-to-end delays?
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Computer Engineering
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Analysis – Design Question 1
End-to-end delays:
(A)
(B)
(C)
(D)
60
100
40
50
20
0
0
Vol Key 2 Audio [ms]
100
Vol Vis. 2 Audio [ms]
1500
100
50
500
0
0
Address Lookup [ms]
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TMC Decode [ms]
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(E)
Analysis – Design Question 2
How robust is architecture A?
Where is the bottleneck of this architecture?
22 MIPS
MMI
(A)
113 MIPS
NAV
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11 MIPS
72 kbps
‹#›
RAD
Computer Engineering
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Analysis – Design Question 2
TMC delay vs. MMI processor speed:
26.4 MIPS
22 MIPS
MMI
(A)
113 MIPS
NAV
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‹#›
11 MIPS
72 kbps
RAD
Computer Engineering
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Analysis – Design Question 3
Architecture D is chosen for further investigation.
How should the processors be dimensioned?
113 MIPS
72 kbps
(D)
130 MIPS
RAD
NAV
MMI
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Analysis – Design Question 3
29 MIPS
113 MIPS
dmax = 200
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dmax = 1000
‹#›
72 kbps
dmax = 50
dmax = 200
33 MIPS
130 MIPS
NAV
RAD
MMI
Computer Engineering
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Overview
Review of General Aspects
Basic Models and Methods
Modular Performance Analysis
Multi-Criteria Optimization
Applications
Concluding Remarks
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Concluding Remarks
SystemC
SystemC
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Acknowledgement and References
The presentation contains contributions by
• Samarjit Chakraborty (NUS)
• Simon Künzli, Ernesto Wandeler, Alexander
Maxiaguine (ETHZ)
• Andreas Herkersdorf, Patricia Sagmeister
(IBM)
• Jonas Greutert (Netmodule)
Many publications are available from
http://www.tik.ee.ethz.ch/~thiele
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Computer Engineering
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