Structured Logic design With VHDL

Logic Chip Design
ดร.ธีรยศ เวียงทอง
ห้อง A502
Course Description
HDL Introduction
HDL Introduction
Modern chip design aspects
Modern chips became too complex
The number of transistors in a modern chip is over a 100 M
Transistor count per chip and chip speed rise up to 50% per year
Estimated time needed for manual implementation
(100 M transistor, 10 sec/transistor) – 135.5 years!!!
HDL Introduction
Modern ASIC design approach
ASIC – Application Specific Integrated Circuit
Modeling system should be designed and described
in the highest abstraction level possible
Simulation and testing at high abstraction level
Conversion of the modeled system
into the low abstraction level model (gate, circuit, silicon level)
using sophisticated synthesis tools
Key point – CAD (Computer Aided Design)
HDL Introduction
Modern ASIC design approach
RTL Model
Simulation & Testing
Gate Level Model
Transistor Level
HDLs (Hardware Description Languages)
are used for system description at the high abstraction level
Verilog vs VHDL
HDL Introduction
VHDL - VHSIC Hardware Description Language
VHSIC - Very High Speed Integrated Circuit
Development of VHDL began in 1983, sponsored by
Department of defense, further developed by the IEEE
and released as IEEE Standard 1076 in 1987
Today it is De facto industry standard for hardware description
Structural Design Concepts
The abstraction hierarchy
The abstraction hierarchy can be expressed in two domains:
structural domain, behavioral domain
Structural domain – component model is described
in terms of an interconnection of more primitive components
Behavioral domain – component model is described
by defining its input/output response
VHDL is used for both structural and behavioral description
Six abstraction hierarchy levels of detail commonly used in design:
silicon, circuit, gate, register, chip and system
Structural Design Concepts
Design process
The design cycle consists of a series of transformations,
synthesis steps:
(1) Transformation from English to an algorithmic representation,
natural language synthesis
(2) Translation from an algorithmic representation
to a data flow representation,
algorithmic synthesis
(3) Translation from data flow representation
to a structural logic gate representation,
logic synthesis
(4) Translation from logic gate to layout and circuit representation,
layout synthesis
Structural Design Concepts
Design process
The design cycle steps can be carried out automatically
in all stages except the first that is currently an active area of research
VHDL tools are used for algorithmic synthesis
Structural Design Concepts
Design tools
Editors – textual (circuit level – SPICE gate, register, chip – VHDL)
or graphic (used at all levels)
Simulators – stochastic (system level)
or deterministic (all levels above the silicon level)
Checkers and Analyzers – employed at all levels, used for example
(1) to insure that the circuit layout
can be fabricated reliably (rule checkers),
(2) to check for the longest path through a logic circuit or system
(timing analyzers)
Synthesizers and Optimizers – improving a form
of the design representation
Basic Features of VHDL
Basic Features of VHDL
Design entities
In VHDL a logic circuit is represented as a design entity
A design entity consists of two different VHDL types of description:
(1) Interface description (reserved word is entity)
(2) One or more architectural bodies (reserved word is architecture)
entity D_FF
defining D FF interface (ports)
architecture of D_FF
specifying the behavior of the entity
Designed digital device
VHDL representation
Basic Features of VHDL
The entity part provides system’s interface specification
as seen from the outside and is generally comprised of:
(1) Parameters (such as bus width or max clock frequency)
(2) Connections (system input and output ports)
entity DesignEntityName is
-- parameters
-- connections
port (ports);
end entity DesignEntityName;
Basic Features of VHDL
Architectural bodies
Architectural bodies are specifying the behavior of the entity
architecture ArchitectureName of DesignEntityName is
-- signal declarations
-- concurrent statements
end architecture ArchitectureName;
There are two types of architectural bodies: algorithmic, structural
Algorithmic - at the beginning of the design process,
designers usually would like to check the accuracy of the algorithm
without specifying the detailed implementation
Structural - the logic design stage, detailed implementation,
entity as a set of interrelated components

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