Report

Delay Evaluation 1. 2. 3. 4. 5. 7/18/2015 Problem Description Total capacitance model Interconnect delay Distributed RC Model Other complications ELEN 689 1 1. Problem Description Given a pair of pins, compute pin-to-pin delay and possibly output waveform Delay Cell Interconnect Cell … Cell 7/18/2015 ELEN 689 2 On-going Research Difficulty: Non-linear behavior of device Complex interconnect parasitic No well-accepted approach Any new idea are welcome 7/18/2015 ELEN 689 3 Circuit Model For an inverter 7/18/2015 ELEN 689 … Csink … Csink 4 Sink Capacitance Gate capacitance, input capacitance, pin capacitance Given for standard cells Can be found using SPICE 7/18/2015 Apply an AC voltage and measure current Average over a range of frequency ELEN 689 I 5 2. Total Capacitance Model Valid for Rd >> Rmetal All fanouts have the same delay RC Rd 7/18/2015 Rd ELEN 689 Ctotal 6 RC Delay 0.35Vdd Vdd Rpd 7/18/2015 ELEN 689 7 Driver Resistors Pull-up and pull-down resistors are not a constant. Which value should we choose? Use SPICE to compute Rpd and Rpd Ids Vds 7/18/2015 ELEN 689 8 RC Delay Assume constant Rpd, t PDf 0.35Vdd Vdd exp R pd (Cout C p ) 1 t PDf R pd (Cout C p ) ln 0.35 R pd (Cout C p ) 7/18/2015 ELEN 689 Zhuo Li pointed out in this case Elmore delay is 35% instead of 50% 9 Linear Delay Delay is linear in Ctotal Rd is pull-up/pull-down resistor, assumed to be linear Interconnect R ignored Common for >0.5um technology standard cells Delay = t0+f*Ctotal 7/18/2015 t0: Intrinsic gate delay f: Load factor ELEN 689 10 Non-Linear: K-factor Consider input transition time tr/f Transition time is signal rising time rising/falling time from 20% to 80% K-factor equation 7/18/2015 Delay td=k(tr/f, Ctotal) Output transition time t’r/f=k’(tr/f, Ctotal) ELEN 689 11 K-Factor … Synopsis K-factor form: Piece-wise-quadratic For each piece, a*tr+b*Ctotal+c*tr*Ctotal+d Obtained from SPICE simulation Ignore interconnect resistance shielding Widely used 7/18/2015 ELEN 689 12 3. Interconnect Delay Consider the first moment of H(s): H(s) h(t)e dt h(t)(1 st )dt st 0 0 0 0 h(t)dt s t h(t)dt 1 m1s 7/18/2015 ELEN 689 13 First Moment Consider h(t) as a probability density function, then m1 is the mean of h(t): m1 t h(t)dt 0 The name moment comes from probability theory 7/18/2015 ELEN 689 14 Mean and Median If impulse response h(t) is symmetric h(t) hstep(t) t t m1 m2 Then the mean of impulse response equals median of step response, which is 50% delay 7/18/2015 ELEN 689 15 Elmore Delay Since m1 is easy to compute, Elmore used m1 as the delay for the RC circuit It can be shown for RC trees, h(t) is skewed to the left. Therefore Elmore delay is always an upper bound on the 50% delay 7/18/2015 ELEN 689 16 Example 1 1 1 1 2 1 1 3 1 4 1 1 m1_1= –4, m1_2= –7, m1_3= –8, m1_4= –8 7/18/2015 ELEN 689 17 Application of Elmore Delay Good Closed form expression, easy to compute Accuracy is better the ramps Useful for routing and placement Bad Inaccurate 7/18/2015 For less than 0.25 um technology Unbalanced RC trees Driver ignored Not useful for timing verification ELEN 689 18 4. Distributed RC Model Metal resistance per unit length is increasing, while gate output resistance is decreasing Portion of delay associated with the interconnect is increasing Due to resistance shielding, total capacitance is an over estimation 7/18/2015 ELEN 689 19 Two Step Approach Cell delay + interconnect delay Cell delay and waveform is computed using K-factor Interconnect delay is computed using Elmore delay or transfer function Cell 7/18/2015 Interconnect ELEN 689 Cell 20 Sink Waveform Given linear input waveform, convolution is easy m ~ h (t) k ie pit i1 Cell Ctotal 7/18/2015 ELEN 689 21 Driving Point Waveform Ctotal is inaccurate. Use load, driving point waveforms match better RC Rd 7/18/2015 Rd ELEN 689 22 K-factor for Load? Given C1,R,C2 of a load, search a table for linear or piece-wise linear waveform Rd 7/18/2015 ELEN 689 23 How to Store Table? Use load, the k-factor table is 4dimensional. Too large! m ~ p i t h (t) k ie i1 Cell 7/18/2015 ELEN 689 24 Effective Capacitance Method Use load Use 2-dimensional K-factor table m ~ p i t h (t) k ie i1 Cell Ceff 7/18/2015 ELEN 689 25 How to Compute Ceff? Basic assumption: there exist an input ramp and Ceff, such that the driving point waveforms are the same Match I and Ie on average Rd I Ie Rd Ceff 7/18/2015 ELEN 689 26 Iteration 1. 2. 3. 4. 7/18/2015 Assume Ceff=Ctotal Use f-factor to find transition time trf Compute current for PI model and Ceff model If equal then stop, otherwise compute new Ceff and go to 2 ELEN 689 27 5. Other Complications Side input Delay from x to out is different for different values on y Need characterize for all input combinations Vdd x out y 7/18/2015 ELEN 689 28 Simultaneous Switching Too many cases to consider Big impact on delay Vdd x out y 7/18/2015 ELEN 689 29 Transistor Sizing Re-sized cells are common Fast techniques to derive k-factor for resized transistors 7/18/2015 ELEN 689 30 Readings on Delay Evaluation J. Rubinstein, P. Penfield Jr., and M. A. Horowitz, “signal delay in RC tree networks,” IEEE Trans. CAD, 1983 F. Dartu, et al., “A gate delay model for high-speed CMOS circuits,” Proc. ICCAD 1994. L. C. Chen, et al., “A new gate delay model for simultaneous switching and its applications,”, Proc. DAC, 2001. E. Acar, et al., “TETA: Transistor-level waveform evaluation for timing analysis,” IEEE Trans. CAD, 2002. 7/18/2015 ELEN 689 31