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Computer Organization Chapter 6 : ARITHMETIC Department of CSE, SSE Mukka www.bookspar.com | Website for students | VTU NOTES Addition and Subtraction of signed numbers Sum si can be implemented with XOR gate. Carry-out function ci+1 can be implemented with a twolevel AND-OR logic circuit. A cascaded connection of n full adder blocks can be used to add two n-bit numbers – called as n-bit ripple carry adder The carry-in C0 into least significant-bit position provides a convenient means of adding 1 to a number For example forming 2’s complement of a number involves adding 1 to 1’s complement of the number www.bookspar.com | Website for students | VTU NOTES xi yi Carry-in ci Sumsi Carry-outci +1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 si = xi yi ci + xi yi ci + xi yi ci + xi yi ci = x i yi ci ci +1 = yi ci + xi ci + xi yi Example: X 7 +Y = +6 Z 13 0 = + 00 1 1 1 1 1 1 1 1 0 0 1 0 1 0 Carry-out ci+1 xi yi si Carry-in ci Legend for stagei Figure 6.1. Logic specification for a stage of binary addition. www.bookspar.com | Website for students | VTU NOTES yi ci xi yi xi ci si ci xi xi yi yi Full adder (FA) ci + 1 ci +1 ci si (a) Logic f xn - 1 cn yn- 1 x1 cn - 1 FA or a single stage y1 s1 (b) An xk n - 1 c kn yk n - 1 y adder s2 n - 1 xn - 1 y n - 1 cn n- bit adder s (k - 1 ) n c0 FA s0 Least significant bit (LSB) position x2 n - 1 y2 n - 1 xn y n n -bit adder sk n - 1 n -bit r ipple-carr y0 c1 FA sn - 1 Most significant bit (MSB) position x0 sn x0 y0 n - bit adder sn - 1 (c) Cascade of k n-bit adders Figure 6.2. Logic for addition of binary vectors. www.bookspar.com | Website for students | VTU NOTES c0 s0 y y n- 1 1 y 0 Add/Sub control x c n- 1 x x 1 0 n-bit adder n c 0 s n- 1 s 1 s 0 Figure 6.3. Binary addition-subtraction logic netw ork. www.bookspar.com | Website for students | VTU NOTES x y i i . . . c i B cell G P i s i i (a) Bit-stage cell x c 3 y x 3 c B cell 4 s G 3 P 2 y x 2 c 3 B cell s 3 G 3 2 P 2 1 y x 1 c 2 B cell s 2 G 1 P 1 y . s 1 G 1 I P 0 I 0 (b) 4-bit adder Figure 6.4. 4-bit carry-lookahead adder. www.bookspar.com | Website for students | VTU NOTES 0 B cell Carry-lookahead logic G 0 0 P 0 0 c 0 x15-12 c16 y15-12 4-bit adder x11-8 c12 P3I x7-4 c8 4-bit adder s15-12 G3I y11-8 y7-4 G2I P2I c4 4-bit adder s11-8 x3-0 s3-0 P1I G0I Carry-lookahead logic G0II . 4-bit adder s7-4 G1I y3-0 P0II Figure 6.5. 16-bit carry-lookahead adder built from 4-bit adders www.bookspar.com | Website for students | VTU NOTES P0I c0