Slide 1

Report
Design and Performance of the
5 GHz Waveform Digitizing Chip
DRS3 for the MEG Experiment
many
Stefan Ritt
Paul Scherrer Institute, Switzerland
Trends in DAQ
• Higher event rates  pile-up
• Baseline estimation event-by-event  removal of 60 Hz noise
• Particle identification by signal shape from PMTs
• Usage of FADCs instead of ADCs/Discriminators/TDCs
• Problems:
• expensive
• high power requirement
hits
• low density
Moving average baseline
2 Nov. '07
IEEE/NSS Honolulu 2007
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Switched Capacitor Array
0.2-2 ns
Inverter “Domino” ring chain
IN
Waveform
stored
Clock
Shift Register
Out
FADC
33 MHz
“Time stretcher” GHz  MHz
Keep Domino wave running in a circular fashion and
stop by trigger  Domino Ring Sampler (DRS)
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IEEE/NSS Honolulu 2007
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Folded Layout
Linear inverter chain causes non-linearity
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IEEE/NSS Honolulu 2007
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Simple inverter chain
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
0
0
1
1
1
1
1
0
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
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Design of Inverter Chain
PMOS > NMOS
PMOS < NMOS
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“Tail Biting”
speed
enable
1
2
3
4
1
2
3
4
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Stopping
speed
enable
1
2
3
4
enable
1
2
3
4
time
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Stop Schematics
WE
1
2
WE
D
Q
D
RES
D
RES
1
2 Nov. '07
Q
3
Q
RES
2
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9
Sample readout
DRS1
Tiny signal
20 pF
0.2 pF
I
DRS2
~kT
Temperature
Dependence
DRS3
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IEEE/NSS Honolulu 2007
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ROI readout mode
delayed trigger
normal
stop
trigger stop after latency
Trigger
Delay
stop
33 MHz
e.g. 100 samples @ 33 MHz
 3 us dead time
(2.5 ns / sample @ 12 channels)
2 Nov. '07
readout shift register
Patent pending!
IEEE/NSS Honolulu 2007
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DRS3
DENABLE
DWRITE
DSPEED
DMODE
• Sampling speed
10 MHz … 5 GHz
• Readout speed
33 MHz, multiplexed
or in parallel
• 50 prototypes received
in July ‘06
WSRCLK
SRIN
WSROUT
SRLOAD
RSRLOAD
RSRCLK
RSRRST
MUX
WRITE SHIFT REGISTER
• 12 ch. each 1024 bins,
6 ch. 2048, …, 1 ch. 12288
IN0+
IN0IN1+
IN1IN2+
IN2IN3+
IN3IN4+
IN4IN5+
IN5IN6+
IN6IN7+
IN7IN8+
IN8IN9+
IN9IN10+
IN10IN11+
IN11-
DOMINO WAVE CIRCUIT
ENABLE
• Fabricated in 0.25 mm
1P5M MMC process
(UMC), 5 x 5 mm2,
radiation hard
DTAP A0 A1 A2 A3
DGND DVDD
CHANNEL 0
MUXOUT /
OUT0
CHANNEL 1
OUT1
CHANNEL 2
OUT2
CHANNEL 3
OUT3
CHANNEL 4
OUT4
CHANNEL 5
OUT5
CHANNEL 6
OUT6
CHANNEL 7
OUT7
CHANNEL 8
OUT8
CHANNEL 9
OUT9
CHANNEL 10
OUT10
CHANNEL 11
OUT11
BIAS
ROFS
STOP SHIFT REGISTER
SSROUT
READ SHIFT REGISTER
RSROUT
AGND AVDD
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IEEE/NSS Honolulu 2007
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DRS3 Test Results
Sampling speed
6
• Unstabilized jitter: ~70ps / turn
30°C
5
• Temperature coefficient: 500ps / ºC
50°C
3
f
SAMP
[GHz]
4
2
1
0
0
0.5
1
1.5
DSPEED [V]
2
2.5
~200 psec
PLL
Vspeed
Reference
Clock (1-4 MHz)
R. Paoletti, N. Turini, R. Pegna, MAGIC collaboration
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IEEE/NSS Honolulu 2007
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Bandwidth + Linearity
Readout chain shows excellent linearity from 0.1V … 1.1V @ 33 MHz reaout
Analog Bandwidth is currently limited by high resistance of on-chip signal bus, will
be increased significantly with DRS4
2
2
1
0
1
-1
AMPLITUE [dB]
NONLINEARITY [mV]
ROFS = 0.95 V
BIAS = 0.70 V
0
0.5 mV max.
-1
-2
-3
-4
-5
-6
450 MHz (-3dB)
-7
-8
-9
-2
0
2 Nov. '07
0.2
0.4
0.6
0.8
ANALOG OUTPUT [V]
1
1.2
-10
1
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10
100
FREQUENCY [MHz]
15
Signal-to-noise ratio
0.52
SNR:
Crosstalk from trigger signal
ANALOG OUTPUT [V]
“Fixed pattern” offset error of 5 mV RMS
can be reduced to 0.35 mV by offset
correction in FPGA
0.51
0.5
0.49
1 V linear range / 0.35 mV = 69 dB (11.5 bits)
0.48
200
200
180
180
140
120
100
80
80
40
20
20
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0.51
0.52
1000
100
40
0.5
OUTPUT VOLTAGE [V]
800
120
60
0.49
400
600
BIN NUMBER
140
60
0
0.48
200
160
OCCURENCE
Offset
Correction
160
OCCURENCE
0
0
0.48
IEEE/NSS Honolulu 2007
0.49
0.5
OUTPUT VOLTAGE [V]
0.51
0.52
16
“Residual charge” problem
R
After sampling a pulse, some residual
charge remains in the capacitors on the next
turn and can mimic wrong pulses
Solution: Clear before write
write
clear
“Ghost pulse”
2% @ 2 GHz
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IEEE/NSS Honolulu 2007
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VPC & USB boards
32 channels input
DRS3
USB interface
board
DRS2
14-bit flash ADC
AD9248
PSI general purpose
VME board with 2 PPC cores
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IEEE/NSS Honolulu 2007
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Availability
32-channel
65 MHz/12bit digitizer
“boosted” by
DRS4 chip to 5 GHz
DRS
MUX
analog front end
trigger
FADC
12 bit
65 MHz
FPGA
LVDS
SRAM
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IEEE/NSS Honolulu 2007
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Conclusions
• 3000 Channels with DRS2 chip running in MEG experiment since 2006
• The DRS3 chip solves temperature
dependence of DRS2 chip, DRS4
solves ghost pulse problem
• The DRS4 chip will be available in
larger quantities beginning 2008
http://midas.psi.ch/drs
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IEEE/NSS Honolulu 2007
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Backup Slides
Complete Domino Cells
Domino Cell 1
Domino Cell 2
Domino Cell 3
Vspeed
Enable
Write
Start
2 Nov. '07
DQ
DQ
DQ
RES
RES
RES
Sampling Cell 1
Sampling Cell 2
IEEE/NSS Honolulu 2007
Sampling Cell 3
22

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