Zhang, Xintong

Report
Process technologies for
making FinFETs
Zhang Xintong
11/26/2014
Outline
• 1. Conventional MOSFET scaling limit
• 2.Structure transformation——FinFETs
• 3.Fabrication process of FinFETs and CMOS integration
• 4.References
Conventional MOSFET scaling limit
Benefits of scaling:
Increase transistor density
Dennard’s scaling law (increase switching
speed, reduce power
dissipation, improve power-delay
product)
Short channel effects:
DIBL effect (Drain induced barrier lowering), the width of the drain-junction
depletion region increases as VD increases, causing the decrease of Vth.
Degradation of the subthreshold slope.
FinFET
Structure transform: Single-gate transistor Multi-gate transistor
a.
b.
c.
d.
e.
f.
SOI FinFET
SOI tri-gate MOSFET
SOI Π-gate MOSFET
SOI Ω-gate MOSFET
SOI gate-all-around MOSFET
Bulk tri-gate MOSFET
Advantage:
Higher drive current
Better electrostatic control (lower off-state
leakage)
Lower supply voltage requirements
FinFET fabrication
First FinFET, fabricated on top of SOI.
Contact: Poly-SiB-doped poly-SiGe
Gate length~20nm, Fin width~15nm,
Fin height~50nm.
The gates are self-aligned and are
aligned to the S/D;
S/D is raised to reduce the parasitic
resistance;
New low-temperature gate or
ultra-thin gate dielectric materials
can be used because they are
deposited after the S/D.
FinFET fabrication
Fin formation(RIE)
Gate stack formation(EBL,etch)
Extension implant(NMOS,As+; PMOS,BF+)
Spacer formation(nitride)
Epitaxial raised source/drain
Deep source/drain implantation
Long channel NMOS <100> FinFETs
have higher G than <110> FinFETs.
Long channel PMOS <100> FinFETs
have lower G than <110> FinFETs.
Lg: 30nm, Tsi: 20nm
Fin height: 65nm
Device optimization
•
Optimize contact-etch-stop-layer and High-K/Metal gate stack  excellent Vth roll-off immunity
•
Silicon surface passivation during HK/MG stack formation
improve interface quality and scale EOT(equivalent oxide
thickness)
•
Strain enhancement techniques(eg. embedded SiGe S/D in PMOS)
 ION and hole mobility improvement
•
Fin pitch reduction
Larger drive current per layout footprint
CMOS FinFETs
Intel has chosen to use bulk substrates
instead of SOI substrates for its 22-nm
tri-gate process.
References
•
1. Ferain I, Colinge C A, Colinge J P. Multigate transistors as the future of classical metal-oxide-semiconductor fieldeffect transistors[J]. Nature, 2011, 479(7373): 310-316.
•
2. Hisamoto D, Lee W C, Kedzierski J, et al. A folded-channel MOSFET for deep-sub-tenth micron era[J]. IEDM Tech.
Dig, 1998, 1998: 1032-1034.
•
3. Chen H Y, Huang C C, Huang C C, et al. Scaling of CMOS FinFETs towards 10 nm[C]//VLSI Technology, Systems,
and Applications, 2003 International Symposium on. IEEE, 2003: 46-48.
•
4. Huang X, Lee W C, Kuo C, et al. Sub 50-nm FinFET: PMOS[C]//Electron Devices Meeting, 1999. IEDM'99.
Technical Digest. International. IEEE, 1999: 67-70.
•
5. Yeh C C, Chang C S, Lin H N, et al. A low operating power FinFET transistor module featuring scaled gate stack and
strain engineering for 32/28nm SoC technology[C]//Electron Devices Meeting (IEDM), 2010 IEEE International. IEEE,
2010: 34.1. 1-34.1. 4.
•
6. Wu C C, Lin D W, Keshavarzi A, et al. High performance 22/20nm FinFET CMOS devices with advanced highK/metal gate scheme[C]//Electron Devices Meeting (IEDM), 2010 IEEE International. IEEE, 2010: 27.1. 1-27.1. 4.
•
7. Kedzierski J, Ieong M, Nowak E, et al. Extension and source/drain design for high-performance FinFET devices[J].
Electron Devices, IEEE Transactions on, 2003, 50(4): 952-958.
•
8. Kavalieros J, Doyle B, Datta S, et al. Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain
engineering[C]//VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on. IEEE, 2006: 50-51.
Thank you!

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